Talk:PDP-8

Clock speed

From the "PDP-8 Maintenance Manual" (F-87, February 1966), "Major States", "Time States" (pg. 1-9, 1-10):

The computer enters one major state during each 1.5 usec computer cycle

Two major time states, .. T1 and T2, occur during each computer cycle (or major state)

and "Clock and TG Flip-Flop" (pg 3-4):

produces standard positive 100-nsec pulses at a rate at a repetition rate of 1,333,333 pps. Each positive pulse complements the TG flip-flop

This is a bit confusing, but it seems that the basic clock is 1.333 MHz, but that there are a pair of those ticks (T1 and T2) during each major state, which agrees with the timing given for major states, which is at a rate of .6666 Mhz.

Given that, as before, "clock speed" should refer to "CPU cycle time", I'd say we should go with 'major state time' for "cycle time".

And maybe we should change the caption in the info-box to say "cycle time", to better inform readers of what the field is? Jnc (talk) 17:35, 20 August 2019 (CEST)

Oh, the major state types which may be traversed during an instruction are:

• Fetch - this may be the only one for simple instructions
• Defer - during indirect addressing
• Execute - all memory reference instructions except JMP
• Word Count - 1st cycle of three cycle data break
• Current Address - 2nd cycle
• Break - 3rd cycle; or single cycle data break

So really most instructions will be one to three major states. Jnc (talk) 18:32, 20 August 2019 (CEST)

OK, I've changed the template; will do the article 'soon' (to give people a chance to comment). Jnc (talk) 14:25, 22 August 2019 (CEST)