Difference between revisions of "MB10 core memory"
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Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35). | Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35). | ||
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Revision as of 12:21, 23 April 2022
The MB10 was a core main memory system for the early PDP-10s, principally the KA10. An MB10 contained 16KW; parity was provided to protect the memory contents. It had an access time of 0.60 μseconds, and a cycle time of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit address form.
It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, and for two-way interleaving (using address bits 21 and 35).
