MF10 core memory

The MF10 was a core main memory system for the mid-period PDP-10s, principally the KI10, although it was also used on early KL10s. It connected to the so-called external memory bus of either the 18-bit or 22-bit address form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a KA10, which uses the 18-bit bus version. An MF10 contained either 32KW or 64KW; parity was provided to protect the memory contents. It had an access time of 0.61 μseconds, and a cycle time of 0.95 µseconds.

It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.

Each port could be independently set for its address, and for either 2- or 4-way interleaving (using address bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively - recall that the PDP-10 uses big-endian numbering, so bit 35 is the low-order bit).

The maintenance manual (A-MN-MF10-0-MAN-1) discloses that the MF10 shares components with the MM11-L core memory of the PDP-11; the H216 core plane of the MF10 is a 19-bit version of the 16-/18-bit H214/H215 of the MM11-L.

External links

• MF10 Core Memory Maintenance Manual