Difference between revisions of "DMA Request and Grant"
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The '''DMA Request''' and '''DMA Grant''' (usually given as their acronyms, '''DMR''' and '''DMG''') are the two [[conductor|lines]] on the [[QBUS]] used in one of the two kinds of [[bus grant|bus requests]] there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. | The '''DMA Request''' and '''DMA Grant''' (usually given as their acronyms, '''DMR''' and '''DMG''') are the two [[conductor|lines]] on the [[QBUS]] used in one of the two kinds of [[bus grant|bus requests]] there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. | ||
Revision as of 03:01, 21 November 2021
The DMA Request and DMA Grant (usually given as their acronyms, DMR and DMG) are the two lines on the QBUS used in one of the two kinds of bus requests there; they are for a device to gain control of the QBUS's data section so that it may perform a DMA cycle.
The CPU may not perform any action (i.e. an interrupt) while the device has control of the bus for a DMA request; a device gaining control of the bus via such a request may perform more than one master-slave cycle before relinquishing control of the bus, however.
DMR is a normal 'wired-OR' broadcast bus line; DMG is a unidirectional grant line. In an QBUS backplane slot, there are a pair of pins for DMG: AR2 for 'DMG In' (BDMGI), and AS2 for 'DMG Out' (BDMGO). In an empty slot there must be a M9047 grant continuity card installed, to carry the grant across that slot.
The UNIBUS has a set of lines with identical functionality, Non-Processor Request and Grant.
