Difference between revisions of "MA10 core memory"
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It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
| − | Each port could be independently set for its address, to disable the low or high 8KW, and for [[interleaving]] (using [[address]] bits 21 and 35). | + | Each port could be independently set for its address, to disable the low or high 8KW, and for [[memory interleaving|interleaving]] (using [[address]] bits 21 and 35). |
==External links== | ==External links== | ||
Latest revision as of 12:53, 2 August 2023
The MA10 was a core main memory system for the early PDP-10s, principally the KA10. An MA10 contained 16KW; parity was provided to protect the memory contents. It had an access time of 0.55 μseconds, and a cycle time of .93 µseconds. It connected to the so-called external memory bus of the 18-bit address form.
It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, to disable the low or high 8KW, and for interleaving (using address bits 21 and 35).
External links
- MA10 Core Memory Maintenance Manual (DEC-10-HIAA-D)
