Scheme Chip: Difference between revisions
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The '''Scheme Chip'''s were a series of VLSI [[LISP machine]] [[microprocessor]]s intended to run [[Scheme]]. | The '''Scheme Chip'''s were a series of VLSI [[LISP machine]] [[microprocessor]]s intended to run [[Scheme]]. There were four generations: SCHEME-78, SCHEME-79, SCHEME-81, and Scheme86. | ||
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* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny] | * [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny] | ||
* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme] | * [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme] | ||
* [https://github.com/larsbrinkhoff/scheme-chip-files Scheme chip files from MIT PDP-10 computers] | |||
[[Category: Microprocessors]] | [[Category: Microprocessors]] | ||
Revision as of 06:08, 2 September 2026
The Scheme Chips were a series of VLSI LISP machine microprocessors intended to run Scheme. There were four generations: SCHEME-78, SCHEME-79, SCHEME-81, and Scheme86.
