Difference between revisions of "Programmable Array Logic"
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| − | '''Programmable Array Logic''' (usually referred to by the acronym, '''PAL''') is the name for a [[integrated circuit|chips]] which contain a class of configurable blocks of [[logic]] elements; the programming is done with [[fusible link]]s. | + | '''Programmable Array Logic''' (usually referred to by the acronym, '''PAL''') is the name for a variety of [[integrated circuit|chips]] which contain a class of configurable blocks of [[logic]] elements; the programming is done with [[fusible link]]s. |
They contain programmable [[array]]s of AND [[gate]]s, whose outputs are led into fixed OR gates. Different models offered different-sized arrays. High-end PALs offered [[registered]] outputs, which could be fed back into the PAL, allowing them to make use of prior state. Some PALs allowed the output of several of the OR gates to be fed into an XOR gate which fed the [[flip-flop|latch]] at the output. | They contain programmable [[array]]s of AND [[gate]]s, whose outputs are led into fixed OR gates. Different models offered different-sized arrays. High-end PALs offered [[registered]] outputs, which could be fed back into the PAL, allowing them to make use of prior state. Some PALs allowed the output of several of the OR gates to be fed into an XOR gate which fed the [[flip-flop|latch]] at the output. | ||
Latest revision as of 18:41, 3 August 2023
Programmable Array Logic (usually referred to by the acronym, PAL) is the name for a variety of chips which contain a class of configurable blocks of logic elements; the programming is done with fusible links.
They contain programmable arrays of AND gates, whose outputs are led into fixed OR gates. Different models offered different-sized arrays. High-end PALs offered registered outputs, which could be fed back into the PAL, allowing them to make use of prior state. Some PALs allowed the output of several of the OR gates to be fed into an XOR gate which fed the latch at the output.
See also
Further reading
- PAL Programmable Array Logic Handbook, Monolithic Memories, Inc., Santa Clara
