Difference between revisions of "Sweet16"
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According to Wozniak, the SWEET16 implementation is a model of frugal coding, taking up only about 300 bytes in memory. SWEET16 runs about 10 times slower than the equivalent native [[MOS Technology 6502|6502]]. | According to Wozniak, the SWEET16 implementation is a model of frugal coding, taking up only about 300 bytes in memory. SWEET16 runs about 10 times slower than the equivalent native [[MOS Technology 6502|6502]]. | ||
| + | |||
| + | The following table is from Byte Magazine, November 1977: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! colspan="8"| SWEET16 OPCODE SUMMARY | ||
| + | |- | ||
| + | ! colspan="4"| Register Ops | ||
| + | ! colspan="4"| Nonregister Ops | ||
| + | |- | ||
| + | | || || || | ||
| + | | 00 || RTN || || (Return to 6502 mode) | ||
| + | |- | ||
| + | | 1n || SET || Rn || Constant (Set) | ||
| + | | 01 || BR || ea || (Branch always) | ||
| + | |- | ||
| + | | 2n || LD || Rn || (Load) | ||
| + | | 02 || BNC || ea || (Branch if No Carry) | ||
| + | |- | ||
| + | | 3n || ST || Rn || (Store) | ||
| + | | 03 || BC || ea || (Branch if Carry) | ||
| + | |- | ||
| + | | 4n || LD || @Rn || (Load indirect) | ||
| + | | 04 || BP || ea || (Branch if Plus) | ||
| + | |- | ||
| + | | 5n || ST || @Rn || (Store indirect) | ||
| + | | 05 || BM || ea || (Branch if Minus) | ||
| + | |- | ||
| + | | 6n || LDD || @Rn || (Load double indirect) | ||
| + | | 06 || BZ || ea || (Branch if Zero) | ||
| + | |- | ||
| + | | 7n || STD || @Rn || (Store double indirect) | ||
| + | | 07 || BNZ || ea || (Branch if NonZero) | ||
| + | |- | ||
| + | | 8n || POP || @Rn || (Pop indirect) | ||
| + | | 08 || BM1 || ea || (Branch if Minus 1) | ||
| + | |- | ||
| + | | 9n || STP || @Rn || (Store pop indirect) | ||
| + | | 09 || BNM1 || ea || (Branch if Not Minus 1) | ||
| + | |- | ||
| + | | An || ADD || Rn || (Add) | ||
| + | | OA || BK || ea || (Break) | ||
| + | |- | ||
| + | | Bn || SUB || Rn || (Sub) | ||
| + | | OB || RS || || (Return from Subroutine) | ||
| + | |- | ||
| + | | Cn || POPD || @Rn || (Pop double indirect) | ||
| + | | 0C || BS || ea || (Branch to Subroutine) | ||
| + | |- | ||
| + | | Dn || CPR || Rn || (Compare) | ||
| + | | 0D || || || (Unassigned) | ||
| + | |- | ||
| + | | En || INA || Rn || (Increment) | ||
| + | | OE || || || (Unassigned) | ||
| + | |- | ||
| + | | Fn || DCR || Rn || (Decrement) | ||
| + | | OF || || || (Unassigned) | ||
| + | |- | ||
| + | |} | ||
== External Links == | == External Links == | ||
* [http://www.6502.org/source/interpreters/sweet16.htm An extensive discussion of the interpreter and source code] | * [http://www.6502.org/source/interpreters/sweet16.htm An extensive discussion of the interpreter and source code] | ||
Revision as of 11:18, 15 February 2013
This is a masterpiece of 6502 programming as far as I'm concerned Lucky 19:06, 17 May 2007 (PDT)
SWEET16 is an interpreted byte-code language invented by Steve Wozniak and implemented as part of the Integer BASIC ROM in the Apple II computer. It was created because Wozniak needed to manipulate 16-bit pointer data in his implementation of BASIC, and the Apple II was an 8-bit computer.
SWEET16 code is executed as if it were running on a (non-existent) 16-bit processor with sixteen, internal 16-bit little-endian registers, R0 through R15. Some registers have well-defined functions:
- R0 is the accumulator.
- R14 is the status register.
- R13 stores the result of all comparison operations for branch testing.
- R15 is the program counter.
The 16 virtual registers, 32 bytes in total, are located in the zero page of the Apple II's real, physical memory map (at $00-$1F). The actual SWEET16 interpreter is located from $F689 to $F7FC.
According to Wozniak, the SWEET16 implementation is a model of frugal coding, taking up only about 300 bytes in memory. SWEET16 runs about 10 times slower than the equivalent native 6502.
The following table is from Byte Magazine, November 1977:
| SWEET16 OPCODE SUMMARY | |||||||
|---|---|---|---|---|---|---|---|
| Register Ops | Nonregister Ops | ||||||
| 00 | RTN | (Return to 6502 mode) | |||||
| 1n | SET | Rn | Constant (Set) | 01 | BR | ea | (Branch always) |
| 2n | LD | Rn | (Load) | 02 | BNC | ea | (Branch if No Carry) |
| 3n | ST | Rn | (Store) | 03 | BC | ea | (Branch if Carry) |
| 4n | LD | @Rn | (Load indirect) | 04 | BP | ea | (Branch if Plus) |
| 5n | ST | @Rn | (Store indirect) | 05 | BM | ea | (Branch if Minus) |
| 6n | LDD | @Rn | (Load double indirect) | 06 | BZ | ea | (Branch if Zero) |
| 7n | STD | @Rn | (Store double indirect) | 07 | BNZ | ea | (Branch if NonZero) |
| 8n | POP | @Rn | (Pop indirect) | 08 | BM1 | ea | (Branch if Minus 1) |
| 9n | STP | @Rn | (Store pop indirect) | 09 | BNM1 | ea | (Branch if Not Minus 1) |
| An | ADD | Rn | (Add) | OA | BK | ea | (Break) |
| Bn | SUB | Rn | (Sub) | OB | RS | (Return from Subroutine) | |
| Cn | POPD | @Rn | (Pop double indirect) | 0C | BS | ea | (Branch to Subroutine) |
| Dn | CPR | Rn | (Compare) | 0D | (Unassigned) | ||
| En | INA | Rn | (Increment) | OE | (Unassigned) | ||
| Fn | DCR | Rn | (Decrement) | OF | (Unassigned) | ||
