Difference between revisions of "QBUS"

From Computer History Wiki
Jump to: navigation, search
m (→‎Pinout: Fix table format)
m (→‎By signal: Blasted wiki table syntax!)
Line 26: Line 26:
 
| Ground || AJ1
 
| Ground || AJ1
 
|-
 
|-
−
Ground || AM1
+
| Ground || AM1
 
|-
 
|-
−
Ground || AT1
+
| Ground || AT1
 
|-
 
|-
−
Ground || AC2
+
| Ground || AC2
 
|-
 
|-
−
Ground || BJ1
+
| Ground || BJ1
 
|-
 
|-
−
Ground || BM1
+
| Ground || BM1
 
|-
 
|-
−
Ground || BT1
+
| Ground || BT1
 
|-
 
|-
−
Ground || BC2
+
| Ground || BC2
 
|-
 
|-
−
+5 || AA2
+
| +5 || AA2
 
|-
 
|-
−
+5 || BV1
+
| +5 || BV1
 
|-
 
|-
−
+5 || BA2
+
| +5 || BA2
 
|-
 
|-
−
+5B || AE1 *
+
| +5B || AE1 *
 
|-
 
|-
−
+5B || AS1 *
+
| +5B || AS1 *
 
|-
 
|-
−
+5B || AV1
+
| +5B || AV1
 
|-
 
|-
−
+12 || AD2
+
| +12 || AD2
 
|-
 
|-
−
+12 || BD2
+
| +12 || BD2
 
|-
 
|-
−
+12B || AS1 *
+
| +12B || AS1 *
 
|-
 
|-
−
+12B || BS1
+
| +12B || BS1
 
|-
 
|-
−
-12 || AB2
+
| -12 || AB2
 
|-
 
|-
−
-12 || BB2
+
| -12 || BB2
  
 
|-
 
|-
−
BDAL00 || AU2
+
| BDAL00 || AU2
 
|-
 
|-
−
BDAL01 || AV2
+
| BDAL01 || AV2
 
|-
 
|-
−
BDAL02 || BE2
+
| BDAL02 || BE2
 
|-
 
|-
−
BDAL03 || BF2
+
| BDAL03 || BF2
 
|-
 
|-
−
BDAL04 || BH2
+
| BDAL04 || BH2
 
|-
 
|-
−
BDAL05 || BJ2
+
| BDAL05 || BJ2
 
|-
 
|-
−
BDAL06 || BK2
+
| BDAL06 || BK2
 
|-
 
|-
−
BDAL07 || BL2
+
| BDAL07 || BL2
 
|-
 
|-
−
BDAL08 || BM2
+
| BDAL08 || BM2
 
|-
 
|-
−
BDAL09 || BN2
+
| BDAL09 || BN2
 
|-
 
|-
−
BDAL10 || BP2
+
| BDAL10 || BP2
 
|-
 
|-
−
BDAL11 || BR2
+
| BDAL11 || BR2
 
|-
 
|-
−
BDAL12 || BS2
+
| BDAL12 || BS2
 
|-
 
|-
−
BDAL13 || BT2
+
| BDAL13 || BT2
 
|-
 
|-
−
BDAL14 || BU2
+
| BDAL14 || BU2
 
|-
 
|-
−
BDAL15 || BV2
+
| BDAL15 || BV2
 
|-
 
|-
−
BDAL16 || AC1
+
| BDAL16 || AC1
 
|-
 
|-
−
BDAL17 || AD1
+
| BDAL17 || AD1
 
|-
 
|-
−
BDAL18 || BC1
+
| BDAL18 || BC1
 
|-
 
|-
−
BDAL19 || BD1
+
| BDAL19 || BD1
 
|-
 
|-
−
BDAL20 || BE1
+
| BDAL20 || BE1
 
|-
 
|-
−
BDAL21 || BF1
+
| BDAL21 || BF1
  
 
|-
 
|-
−
BBS7 || AP2
+
| BBS7 || AP2
 
|-
 
|-
−
BDIN || AH2
+
| BDIN || AH2
 
|-
 
|-
−
BDOUT || AE2
+
| BDOUT || AE2
 
|-
 
|-
−
BREF || AR1
+
| BREF || AR1
 
|-
 
|-
−
BRPLY || AF2
+
| BRPLY || AF2
 
|-
 
|-
−
BSACK || BN1
+
| BSACK || BN1
 
|-
 
|-
−
BSYNC || AJ2
+
| BSYNC || AJ2
 
|-
 
|-
−
BWTBT || AK2
+
| BWTBT || AK2
  
 
|-
 
|-
−
BDCOK || BA1
+
| BDCOK || BA1
 
|-
 
|-
−
BEVNT || BR1
+
| BEVNT || BR1
 
|-
 
|-
−
BHALT || AP1
+
| BHALT || AP1
 
|-
 
|-
−
BINIT || AT2
+
| BINIT || AT2
 
|-
 
|-
−
BPOK || BB1
+
| BPOK || BB1
  
 
|-
 
|-
−
BDMGI || AR2
+
| BDMGI || AR2
 
|-
 
|-
−
BDMGO || AS2
+
| BDMGO || AS2
 
|-
 
|-
−
BDMR || AN1
+
| BDMR || AN1
 
|-
 
|-
−
BIAKI || AM2
+
| BIAKI || AM2
 
|-
 
|-
−
BIAKO || AN2
+
| BIAKO || AN2
 
|-
 
|-
−
BIRQ4 || AL2
+
| BIRQ4 || AL2
 
|-
 
|-
−
BIRQ5 || AA1
+
| BIRQ5 || AA1
 
|-
 
|-
−
BIRQ6 || AB1
+
| BIRQ6 || AB1
 
|-
 
|-
−
BIRQ7 || BP1
+
| BIRQ7 || BP1
  
 
|-
 
|-
−
SRUN || AH1 *
+
| SRUN || AH1 *
  
 
|-
 
|-
−
ASpare2 || BU1
+
| ASpare2 || BU1
 
|-
 
|-
−
MSpareA || AK1
+
| MSpareA || AK1
 
|-
 
|-
−
MSpareB || AL1
+
| MSpareB || AL1
 
|-
 
|-
−
MSpareB || BK1
+
| MSpareB || BK1
 
|-
 
|-
−
MSpareB || BL1
+
| MSpareB || BL1
 
|-
 
|-
−
PSpare1 || AU1
+
| PSpare1 || AU1
 
|-
 
|-
−
PSpare2 || BU1
+
| PSpare2 || BU1
 
|-
 
|-
−
PSpare4 || BS1
+
| PSpare4 || BS1
 
|-
 
|-
−
SSpare1 || AE1 *
+
| SSpare1 || AE1 *
 
|-
 
|-
−
SSpare2 || AF1
+
| SSpare2 || AF1
 
|-
 
|-
−
SSpare3 || AH1 *
+
| SSpare3 || AH1 *
 
|-
 
|-
−
SSpare8 || BH1
+
| SSpare8 || BH1
 
|}
 
|}
  

Revision as of 20:08, 17 December 2015

The QBUS, previously known as the "LSI-11 bus", was intended as a cheaper alternative to the UNIBUS system by Digital Equipment Corporation.

It was widely used in PDP-11s and VAXen.

The bus had multiplexed address and data lines, and was available in 16-, 18-, and 22-address-bit configurations (data width remained 16 bits in all three versions).

Important note: The 16-bit and 18/22-bit backplanes are electrically incompatible and mixing the two may damage cards on the bus.

It is possible to upgrade 18-bit backplanes to 22-bit; see Upgrading QBUS backplanes.

Signalling

Like the UNIBUS, there are three basic kinds of cycles on the QBUS: data read/write cycles (in which a 'master' reads or writes data to/from a 'slave', which is usually, but not always, memory); DMA cycles (in which a device gains control of the bus so that it can do a read/write cycle); and interrupt cycles, in which a device causes the CPU to perform an interrupt.

All QBUS transactions are asynchronous, and use interlocked request/response signals for control and timing.

Pinout

QBUS pins are identified in the standard UNIBUS manner; there are two connectors, A and B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet', A-V, with G, I, O and Q dropped.

By signal

Signal Pin
Ground AJ1
Ground AM1
Ground AT1
Ground AC2
Ground BJ1
Ground BM1
Ground BT1
Ground BC2
+5 AA2
+5 BV1
+5 BA2
+5B AE1 *
+5B AS1 *
+5B AV1
+12 AD2
+12 BD2
+12B AS1 *
+12B BS1
-12 AB2
-12 BB2
BDAL00 AU2
BDAL01 AV2
BDAL02 BE2
BDAL03 BF2
BDAL04 BH2
BDAL05 BJ2
BDAL06 BK2
BDAL07 BL2
BDAL08 BM2
BDAL09 BN2
BDAL10 BP2
BDAL11 BR2
BDAL12 BS2
BDAL13 BT2
BDAL14 BU2
BDAL15 BV2
BDAL16 AC1
BDAL17 AD1
BDAL18 BC1
BDAL19 BD1
BDAL20 BE1
BDAL21 BF1
BBS7 AP2
BDIN AH2
BDOUT AE2
BREF AR1
BRPLY AF2
BSACK BN1
BSYNC AJ2
BWTBT AK2
BDCOK BA1
BEVNT BR1
BHALT AP1
BINIT AT2
BPOK BB1
BDMGI AR2
BDMGO AS2
BDMR AN1
BIAKI AM2
BIAKO AN2
BIRQ4 AL2
BIRQ5 AA1
BIRQ6 AB1
BIRQ7 BP1
SRUN AH1 *
ASpare2 BU1
MSpareA AK1
MSpareB AL1
MSpareB BK1
MSpareB BL1
PSpare1 AU1
PSpare2 BU1
PSpare4 BS1
SSpare1 AE1 *
SSpare2 AF1
SSpare3 AH1 *
SSpare8 BH1

Signals marked with a "*" show cases where two signals use the same pin (not at the same time, obviously).

By pin

 BIRQ5		AA1  (old BSpare1)
 BIRQ6		AB1  (old BSpare2)
 BDAL16	AC1  (old BSpare3)
 BDAL17	AD1  (old BSpare4)
 SSpare1	AE1  (alt +5B)
 SSpare2	AF1  (alt SRUN/SMENBL on CF1)
 SSpare3	AH1  (alt SRUN on CH1)
 Ground	AJ1
 MSpareA	AK1
 MSpareB	AL1
 Ground	AM1
 BDMR		AN1
 BHALT		AP1
 BREF		AR1
 +5B/+12B	AS1  (old PSpare3)
 Ground	AT1
 PSpare1	AU1
 +5B		AV1
 
 +5		AA2
 -12/-5	AB2
 Ground	AC2
 +12		AD2
 BDOUT		AE2
 BRPLY		AF2
 BDIN		AH2
 BSYNC		AJ2
 BWTBT		AK2
 BIRQ4		AL2 (was BIRQ)
 BIAKI		AM2
 BIAKO		AN2
 BBS7		AP2
 BDMGI		AR2
 BDMGO		AS2
 BINIT		AT2
 BDAL00	AU2
 BDAL01	AV2
 
 
 BDCOK		BA1
 BPOK		BB1
 BDAL18	BC1 (old SSpare4)
 BDAL19	BD1 (old SSpare5)
 BDAL20	BE1 (old SSpare6)
 BDAL21	BF1 (old SSpare7)
 SSpare8	BH1
 Ground	BJ1
 MSpareB	BK1
 MSpareB	BL1
 Ground	BM1
 BSACK		BN1
 BIRQ7		BP1  (old PSpare6)
 BEVNT		BR1
 PSpare4/+12B	BS1
 Ground	BT1
 PSpare2	BU1
 +5		BV1
 
 +5		BA2
 -12/-5	BB2
 Ground	BC2
 +12		BD2
 BDAL02	BE2
 BDAL03	BF2
 BDAL04	BH2
 BDAL05	BJ2
 BDAL06	BK2
 BDAL07	BL2
 BDAL08	BM2
 BDAL09	BN2
 BDAL10	BP2
 BDAL11	BR2
 BDAL12	BS2
 BDAL13	BT2
 BDAL14	BU2
 BDAL15	BV2
Retrieved from "https://gunkies.org/w/index.php?title=QBUS&oldid=11349"