Private Memory Interconnect

The Private Memory Interconnect (PMI) bus was a high-performance memory bus, a variant of the QBUS, introduced with the KDJ11-B PDP-11 CPU. It also provides means for the CPU and a KTJ11-B UNIBUS adapter to communicate in providing UNIBUS service.

For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte reads; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.

The PMI uses the CD interconnect specified for QBUS backplanes to carry PMI-specific signals; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Use of the standard CD interconnect means that PMI-systems (such as a PDP-11/83 can be constructed with a standard Q/CD backplane, a KDJ11-B CPU card, and one or more PMI memories.

Pinout

PMI pins are identified in the standard UNIBUS manner; there are four connectors, A-B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet', A-V, with G, I, O and Q dropped.

The tables below show the pins used for normal PMI master-slave cycles (as in the PDP-11/83), and those used to communicate with the KTJ11-B UNIBUS adapter (PDP-11/84 and PDP-11/94 only).

Master-slave signals

Pin	Signal	Meaning
CE1	PBCYC	Indicates a PMI cycle
CR1	PBSY	PMI busy
DC1	PBYT	Used with BWTBT to indicate type of PMI cycle
CP1	PBLKM	Indicates a PMI block mode transfer (i.e. multi-word)
CB1	PSSEL	Slave select
DB1	PWTSTB	Write strobe
CJ1	PSBFUL	Slave buffer full
CM1	PRDSTB	Read strobe
CH1	PHBPAR	High byte parity
CK1	PLBPAR	Low byte parity

UNIBUS adapter communication signals

Pin	Signal	Meaning
CF1	PUBSYS	UNIBUS adapter present
DD1	PMAPE	Enable UNIBUS map for UNIBUS->PMI
CD1	PUBMEM	CPU access to UNIBUS
CV1	PUBTMO	UNIBUS timeout