Difference between revisions of "Open collector"
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| − | '''Open collector''' refers to a common output type in [[transistor-transistor logic|TTL]], e.g. the [[74 series]] of [[integrated circuit]]s. In it, the [[transistor|collectors]] of the [[transistor]]s which make up the | + | '''Open collector''' refers to a common output type in [[transistor-transistor logic|TTL]], e.g. the [[74 series]] of [[integrated circuit]]s. In it, the [[transistor|collectors]] of the [[transistor]]s which make up the [[gate]]s, which are usually the output of the gates, are not connected to the power [[voltage]] (usually through a [[resistor]]), but rather are left un-connected, or 'open' (hence the name). |
This allows the creation of so-called 'wired-AND' (in [[positive logic]]) and 'wired-OR' (in [[negative logic]]) functions by simply connecting together the outputs of the gates (which must be open-collector) which produce the signals which are to be ANDed or ORed (as the case may be) together. A pull-up resistor to the supply voltage completes the 'gate'. | This allows the creation of so-called 'wired-AND' (in [[positive logic]]) and 'wired-OR' (in [[negative logic]]) functions by simply connecting together the outputs of the gates (which must be open-collector) which produce the signals which are to be ANDed or ORed (as the case may be) together. A pull-up resistor to the supply voltage completes the 'gate'. | ||
Revision as of 17:44, 27 March 2018
Open collector refers to a common output type in TTL, e.g. the 74 series of integrated circuits. In it, the collectors of the transistors which make up the gates, which are usually the output of the gates, are not connected to the power voltage (usually through a resistor), but rather are left un-connected, or 'open' (hence the name).
This allows the creation of so-called 'wired-AND' (in positive logic) and 'wired-OR' (in negative logic) functions by simply connecting together the outputs of the gates (which must be open-collector) which produce the signals which are to be ANDed or ORed (as the case may be) together. A pull-up resistor to the supply voltage completes the 'gate'.
As TTL gates produce low outputs by sinking current to ground (drawing it in through the output, seemingly paradoxically), any of the gates in the wired-AND/OR can force the output low by turning on.
Normal TTL gates cannot be connected together in this manner since if one gate tries to produce a high output, and another a low, the two will 'clash'.
