Difference between revisions of "Conditional branch"
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A '''conditional branch''' is an [[instruction]] in the [[Central Processing Unit|CPU]] which is not always taken; whether it is taken or not depends on some test. | A '''conditional branch''' is an [[instruction]] in the [[Central Processing Unit|CPU]] which is not always taken; whether it is taken or not depends on some test. | ||
| − | In | + | In modern computers, conditional branches are usually implemented with [[condition codes]], status bits set by previous arithmetic operations. By examining these bits, the complete complement of signed and unsigned conditional branches can be produced. |
==Example set== | ==Example set== | ||
Latest revision as of 18:41, 25 December 2018
A conditional branch is an instruction in the CPU which is not always taken; whether it is taken or not depends on some test.
In modern computers, conditional branches are usually implemented with condition codes, status bits set by previous arithmetic operations. By examining these bits, the complete complement of signed and unsigned conditional branches can be produced.
Example set
On the PDP-11, the rather complete set of conditional branches (copied in many machines since) includes:
- BEQ - Zero, or equal (after comparing two quantities)
- BNE - Non-zero, or not equal
- BPL - Positive
- BMI - Negative
- BCS - Carry
- BCC - No Carry
- BVS - Overflow
- BVC - No Oveflow
Signed:
- BGE - Greater or Equal
- BGT - Greater
- BLE - Lesser or Equal
- BLT - Lesser
Unsigned:
- BLOS - Lower or the same
- BLO - Lower
- BHIS - Higher or the same
- BHI - Higher
