Difference between revisions of "MB10 core memory"
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It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
| − | Each port could be independently set for two-way [[interleaving]] | + | Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35). |
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 03:17, 6 March 2019
The MB-10 was a main memory system for the early PDP-10s, principally the KA10. An MB10 contained 16KW, and had a cycle time of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit address form.
It was a multi-port memory, with 4 ports per memory system: the CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, and for two-way interleaving (using address bits 21 and 35).
