Difference between revisions of "MA10 core memory"
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| − | The '''MA10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form. | + | The '''MA10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form. |
It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
Revision as of 03:32, 7 March 2019
The MA10 was a core main memory system for the early PDP-10s, principally the KA10. An MA10 contained 16KW, and had a cycle time of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit address form.
It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, to disable the low or high 8KW, and for interleaving (using address bits 21 and 35).
