Difference between revisions of "PDP-10 memories"
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| − | There were three generations of [[main memory]] systems for the [[PDP-10]]; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively | + | There were three generations of [[main memory]] [[bus]], and memory systems to attach to them, for the [[PDP-10]] line; the first two with the so-called external memory bus, in 18- and 22-bit [[address]] forms (for the [[KA10]]. and [[KI10]] and early [[KL10]], respectively), and the last with the internal 'S-Bus' (for the later KL10). (Memory for the [[KS10]], which was ''sui generis'', is not covered here.) |
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| + | There were minor differences between the two external bus types, requiring a [[KI10-M Memory Bus Adapter]] if 18-bit units are to be attached to a KI10. Similarly, 22-bit units can be attached to the S-Bus using a [[DMA20 Memory Bus Controller]]. | ||
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| + | The S-Bus (and a later version, the X-Bus, used with [[Metal Oxide Semiconductor|MOS]] internal memory, such as the MF20) can do block transfers of up to four [[word]]s; the block can start with any word within the block. | ||
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| + | ==Memory systems== | ||
18-bit external: | 18-bit external: | ||
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* [[MG20 MOS memory|MG20]] | * [[MG20 MOS memory|MG20]] | ||
| − | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. All except the MF20 and MG20 were [[core memory]], and almost all supported [[parity]], and some level of [[interleaving]]. | + | The first two groups are all [[multi-port memory]] (generally 4 ports per memory system in the first group, and 8 in the second); the [[Central Processing Unit|CPU]] uses one port, the others are used by [[channel]]s for [[mass storage]] such as [[disk]]s. All except the MF20 and MG20 were [[core memory]], and almost all supported [[parity]], and some level of [[interleaving]]. |
[[Category: PDP-10 memories]] | [[Category: PDP-10 memories]] | ||
Revision as of 16:02, 23 March 2019
There were three generations of main memory bus, and memory systems to attach to them, for the PDP-10 line; the first two with the so-called external memory bus, in 18- and 22-bit address forms (for the KA10. and KI10 and early KL10, respectively), and the last with the internal 'S-Bus' (for the later KL10). (Memory for the KS10, which was sui generis, is not covered here.)
There were minor differences between the two external bus types, requiring a KI10-M Memory Bus Adapter if 18-bit units are to be attached to a KI10. Similarly, 22-bit units can be attached to the S-Bus using a DMA20 Memory Bus Controller.
The S-Bus (and a later version, the X-Bus, used with MOS internal memory, such as the MF20) can do block transfers of up to four words; the block can start with any word within the block.
Memory systems
18-bit external:
22-bit external:
Internal:
The first two groups are all multi-port memory (generally 4 ports per memory system in the first group, and 8 in the second); the CPU uses one port, the others are used by channels for mass storage such as disks. All except the MF20 and MG20 were core memory, and almost all supported parity, and some level of interleaving.
