MG20 MOS memory

The MG20 was a MOS DRAM main memory system for the later PDP-10s, principally the final KL10s (models KL10-E and KL10-R). An MG20 contained up to two storage groups, each with 1MW, for a maximum of 2MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M.

The MG20 was basically an MF20 with 64Kx1 chips, instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the power supply; the four control cards of the MF20:

• M8574 Write Path
• M8575 Syndrome
• M8576 Control and Timing
• M8577 Address and Timing

remained unchanged.

ECC is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was single-port memory, and could not be used in symmetric multi-processor systems, or with external channels.