Difference between revisions of "LH-DH/11 Local/Distant Host Controller"
From Computer History Wiki
(Basics) |
(→0767600: Control & Status In Register (CSRI): add bits) |
||
Line 29: | Line 29: | ||
| ERR || NXM || EOM || Unused || HR || INR || RMRE || IDBF || RDY || IE || colspan=2 | XBA16-17 || SENB || HRC || IRST || GO | | ERR || NXM || EOM || Unused || HR || INR || RMRE || IDBF || RDY || IE || colspan=2 | XBA16-17 || SENB || HRC || IRST || GO | ||
{{16bit-bitout}} | {{16bit-bitout}} | ||
+ | |||
+ | * ERR - Error Flag | ||
+ | * NXM - Non-Existent Memory | ||
+ | * EOM - End of Message | ||
+ | * HR - Host Ready | ||
+ | * INR - IMP Not Ready | ||
+ | * RMRE - Receive Master Ready Error | ||
+ | * IDBF - Input Data Buffer Full | ||
+ | * RDY - Device Ready | ||
+ | * IE - Interrupt Enable | ||
+ | * SENB - Store Enable | ||
+ | * HRC - Host Relay Control | ||
+ | * IRST - Input Interface Reset | ||
===0767602: Data Buffer In Register (DBRI)=== | ===0767602: Data Buffer In Register (DBRI)=== |
Revision as of 05:06, 30 October 2021
The LH-DH/11 Local/Distant Host Controller is a DMA UNIBUS IMP interface produced by ACC to allow a UNIBUS machine to connect to an ARPANET IMP.
It consists of a 10-1/2" rack mounting box holding a pair of wire-wraped boards (one for packet input, and one for output), holding a number of SSI TTL integrated circuits; there is also an internal power supply. Level converters allow use as either a Local Host or Distant Host interface; BC11A cables connect it to the rest of the system.
Contents
- 1 Registers
- 1.1 0767600: Control & Status In Register (CSRI)
- 1.2 0767602: Data Buffer In Register (DBRI)
- 1.3 0767604: Current Word Address In Register (CWAI)
- 1.4 0767606: Word Count In Register (WCI)
- 1.5 0767610: Control & Status Out Register (CSRO)
- 1.6 0767612: Data Buffer Out Register (DBRO)
- 1.7 0767614: Current Word Address Out Register (CWAO)
- 1.8 0767616: Word Count Out Register (WCO)
- 2 External links
Registers
Register | Abbreviation | Address |
---|---|---|
Control & Status In Register | CSRI | 0767600 |
Data Buffer In Register | DBRI | 0767602 |
Current Word Address In Register | CWAI | 0767604 |
Word Count In Register | WCI | 0767606 |
Control & Status Out Register | CSRO | 0767610 |
Data Buffer Out Register | DBRO | 0767612 |
Current Word Address Out Register | CWAO | 0767614 |
Word Count Out Register | WCO | 0767616 |
0767600: Control & Status In Register (CSRI)
ERR | NXM | EOM | Unused | HR | INR | RMRE | IDBF | RDY | IE | XBA16-17 | SENB | HRC | IRST | GO | |
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
- ERR - Error Flag
- NXM - Non-Existent Memory
- EOM - End of Message
- HR - Host Ready
- INR - IMP Not Ready
- RMRE - Receive Master Ready Error
- IDBF - Input Data Buffer Full
- RDY - Device Ready
- IE - Interrupt Enable
- SENB - Store Enable
- HRC - Host Relay Control
- IRST - Input Interface Reset
0767602: Data Buffer In Register (DBRI)
Data15 <---> Data00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767604: Current Word Address In Register (CWAI)
WA15 <---> WA00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767606: Word Count In Register (WCI)
WC15 <---> WC00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767610: Control & Status Out Register (CSRO)
ERR | NXM | WC0 | Unused | TMRE | ODBE | RDY | IE | XBA16-17 | BBM | ELB | IRST | GO | |||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767612: Data Buffer Out Register (DBRO)
Data15 <---> Data00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767614: Current Word Address Out Register (CWAO)
WA15 <---> WA00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
0767616: Word Count Out Register (WCO)
WC15 <---> WC00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |