Difference between revisions of "MF20 MOS memory"
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* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622) | * [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622) | ||
| − | [[Category: PDP-10 | + | [[Category: PDP-10 Memories]] |
Revision as of 13:47, 22 April 2022
The MF20 was a MOS DRAM main memory system for the later PDP-10s, principally the final KL10s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.
The access time is .80 µseconds at the CPU, and the cycle time is 1.00 µseconds (both for the first word in a 4-word block). The MF20 connected to the KL10's upgraded internal memory bus, the X-Bus. ECC is provided to protect the memory contents; an MF20 44-bit word contains 36 data bits, 6 ECC bits, 1 bit of ECC parity, and 1 spare bit. The MF20 can be configured to switch the spare bit in to temporarily replace a failing bit, until the latter can be replaced
The sizes above are with 16Kx1 chips; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the MG20 MOS memory.
External links
- MOS Memory Subsystem Technical Manual (EK-0MF20-TM)
- MF20 Field Maintenance Print Set (MP00622)
