Difference between revisions of "Extended Memory Interconnect"
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The Extended Memory Interconnect (acronym: XMI) was a bus introduced with the [[VAX 6000 series]] of [[Digital Equipment Corporation|DEC]] computers to cope with increased requirements, e.g bandwidth. | The Extended Memory Interconnect (acronym: XMI) was a bus introduced with the [[VAX 6000 series]] of [[Digital Equipment Corporation|DEC]] computers to cope with increased requirements, e.g bandwidth. | ||
| + | == XMI Overview == | ||
| + | The XMI is the primary interconnect for the [[VAX 6000 Model 200|VAX 6200]] system. The XMI supports multiple processors, multiple memory modules, and multiple I/O adapters. | ||
| + | |||
| + | Figure 2-1 shows a four-processor VAX 6200 system. | ||
| + | |||
| + | [[File:VAX 6200 Four-Processor System Block Diagram.png]] | ||
| + | |||
| + | The XMI consists of the electrical environment of the XMI bus, the protocol observed by a node on the bus, the backplane, and the logic used to implement the protocol. | ||
| + | |||
| + | The XMI bus is limited length, pended, and synchronous with centralized arbitration. Several transactions can be in progress at a given time, allowing highly efficient use of the bus bandwidth. Arbitration and data transfers can occur simultaneously. | ||
| + | |||
| + | The bus supports: | ||
| + | * Quadword-, octaword-, and hexword-length reads to memory | ||
| + | * Quadword- and octaword-length memory writes | ||
| + | * Longword-length read and write operations to I/O space | ||
| + | |||
| + | The longword operations implement byte and word modes required by certain I/O devices. | ||
| + | |||
| + | The XMI has a 64 ns bus cycle. | ||
| + | |||
| + | The XMI has a bandwidth of 100 Mbytes per second; however, the usable bandwidth depends on transaction length: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | | colspan="2" style="text-align:center;" | '''Usable XMI Bandwidth''' | ||
| + | |- | ||
| + | | '''Operation''' || '''Bandwidth (Mbytes/second)''' | ||
| + | |- | ||
| + | | Longword (4 bytes) Read || 31.25 | ||
| + | |- | ||
| + | | Quadword (8 bytes) Read || 62.50 | ||
| + | |- | ||
| + | | Octaword (16 bytes) Read || 83.30 | ||
| + | |- | ||
| + | | Hexword (32 bytes) Read || 100.00 | ||
| + | |- | ||
| + | | Longword Write || 31.25 | ||
| + | |- | ||
| + | | Quadword Write || 62.50 | ||
| + | |- | ||
| + | | Octaword Write || 83.30 | ||
| + | |} | ||
| + | |||
| + | == XMI Versions == | ||
The XMI bus started with the "+5V '''XMI-1'''" version which was developed to the "+3.3V '''XMI-2'''" version later on. | The XMI bus started with the "+5V '''XMI-1'''" version which was developed to the "+3.3V '''XMI-2'''" version later on. | ||
| Line 7: | Line 50: | ||
The upgrade adds +3.3 volt power, an XMI-2 [[backplane]] preassembled with bus bars and cables, and an H7206-B power and logic unit. | The upgrade adds +3.3 volt power, an XMI-2 [[backplane]] preassembled with bus bars and cables, and an H7206-B power and logic unit. | ||
| − | [http://www.vaxhaven.com/images/f/fc/EK-650EB-UP-002.pdf EK-650EB-UP-002 VAX 6000 XMI Conversion Manual] describes the upgrade procedure. | + | The manual [http://www.vaxhaven.com/images/f/fc/EK-650EB-UP-002.pdf EK-650EB-UP-002 VAX 6000 XMI Conversion Manual] describes the upgrade procedure. |
| − | {{stub}} | + | {{semi-stub}} |
[[Category: DEC Buses]] | [[Category: DEC Buses]] | ||
[[Category: XMI]] | [[Category: XMI]] | ||
Revision as of 12:35, 17 July 2022
The Extended Memory Interconnect (acronym: XMI) was a bus introduced with the VAX 6000 series of DEC computers to cope with increased requirements, e.g bandwidth.
XMI Overview
The XMI is the primary interconnect for the VAX 6200 system. The XMI supports multiple processors, multiple memory modules, and multiple I/O adapters.
Figure 2-1 shows a four-processor VAX 6200 system.
The XMI consists of the electrical environment of the XMI bus, the protocol observed by a node on the bus, the backplane, and the logic used to implement the protocol.
The XMI bus is limited length, pended, and synchronous with centralized arbitration. Several transactions can be in progress at a given time, allowing highly efficient use of the bus bandwidth. Arbitration and data transfers can occur simultaneously.
The bus supports:
- Quadword-, octaword-, and hexword-length reads to memory
- Quadword- and octaword-length memory writes
- Longword-length read and write operations to I/O space
The longword operations implement byte and word modes required by certain I/O devices.
The XMI has a 64 ns bus cycle.
The XMI has a bandwidth of 100 Mbytes per second; however, the usable bandwidth depends on transaction length:
| Usable XMI Bandwidth | |
| Operation | Bandwidth (Mbytes/second) |
| Longword (4 bytes) Read | 31.25 |
| Quadword (8 bytes) Read | 62.50 |
| Octaword (16 bytes) Read | 83.30 |
| Hexword (32 bytes) Read | 100.00 |
| Longword Write | 31.25 |
| Quadword Write | 62.50 |
| Octaword Write | 83.30 |
XMI Versions
The XMI bus started with the "+5V XMI-1" version which was developed to the "+3.3V XMI-2" version later on.
There was an upgrade kit option H9657-CU that takes a VAX 6000 Model 200, 300, or 400 system with an XMI-1 power system and upgrades it to a VAX 6000 Model 500 with an XMI-2 power system.
The upgrade adds +3.3 volt power, an XMI-2 backplane preassembled with bus bars and cables, and an H7206-B power and logic unit.
The manual EK-650EB-UP-002 VAX 6000 XMI Conversion Manual describes the upgrade procedure.
