Template:Infobox CPU: Difference between revisions
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m Fixed typos in description |
Allow this one to set the image size too |
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name = formal name of of the CPU | name = formal name of of the CPU | ||
image = image | image = image | ||
caption = | |||
imgwidth = size of image (default 250px) | |||
manufacturer = | manufacturer = | ||
architecture = 8-bit, 16-bit, 32/64-bit etc. general instruction set | architecture = 8-bit, 16-bit, 32/64-bit etc. general instruction set | ||
family = | family = if part of a family (e.g. as the 68040 is family mc68k) | ||
year introduced = | year introduced = | ||
year discontinued = | year discontinued = | ||
| Line 15: | Line 17: | ||
cache = | cache = | ||
registers = number of registers | registers = number of registers | ||
clock speed = | clock speed = either CPU cycle time in ns/µs/etc, or (preferably) MHz. | ||
pipeline depth = number of pipeline stage, if applicable | pipeline depth = number of pipeline stage, if applicable | ||
</pre> | </pre> | ||
</noinclude> | </noinclude> | ||
<includeonly> | <includeonly> | ||
{| class="infobox bordered" style="width: 25em; text-align: left; font-size: 90%" align="right" | {| class="infobox bordered" style="width: 25em; text-align: left; font-size: 90%" align="right" | ||
| Line 25: | Line 28: | ||
|- | |- | ||
{{#if: {{{image|}}} | | {{#if: {{{image|}}} | | ||
{{!}} colspan="2" style="text-align:center;" {{!}} [[Image:{{{image}}}|250px| ]]<br>{{{caption}}} }} | {{!}} colspan="2" style="text-align:center;" {{!}} [[Image:{{{image}}}|{{{imgwidth|250px}}}| ]]<br>{{{caption}}} }} | ||
|- | |- | ||
Revision as of 15:34, 8 February 2024
This template is for describing a CPU
name = formal name of of the CPU image = image caption = imgwidth = size of image (default 250px) manufacturer = architecture = 8-bit, 16-bit, 32/64-bit etc. general instruction set family = if part of a family (e.g. as the 68040 is family mc68k) year introduced = year discontinued = address bus = number of bits (8-bit, 16-bit, 32-bit, 64-bit..) data bus = number of bits instructions = number of instructions cache = registers = number of registers clock speed = either CPU cycle time in ns/µs/etc, or (preferably) MHz. pipeline depth = number of pipeline stage, if applicable
