Difference between revisions of "Instruction set architecture"
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| − | An '''instruction set architecture''' (the term is usually given as the acronym, '''ISA''') is an [[instruction set]] design shared across multiple [[Central Processing Unit|CPU]] implementations (thereby making [[object code]] [[portable]] across them, allowing them to share [[compiler]]s, etc). | + | An '''instruction set architecture''' (the term is usually given as the acronym, '''ISA'''; sometimes given as '''instruction set processor''', or '''ISP''') is an [[instruction set]] design shared across multiple [[Central Processing Unit|CPU]] implementations (thereby making [[object code]] [[portable]] across them, allowing them to share [[compiler]]s, etc). |
Perhaps the most famous example was the first, the [[IBM System/360]] (initially shared across a dozen models in the line, and still in use today), which cemented [[International Business Machines|IBM]]'s place atop the early computer industry. Other examples include: | Perhaps the most famous example was the first, the [[IBM System/360]] (initially shared across a dozen models in the line, and still in use today), which cemented [[International Business Machines|IBM]]'s place atop the early computer industry. Other examples include: | ||
Latest revision as of 20:44, 19 May 2024
An instruction set architecture (the term is usually given as the acronym, ISA; sometimes given as instruction set processor, or ISP) is an instruction set design shared across multiple CPU implementations (thereby making object code portable across them, allowing them to share compilers, etc).
Perhaps the most famous example was the first, the IBM System/360 (initially shared across a dozen models in the line, and still in use today), which cemented IBM's place atop the early computer industry. Other examples include:
