Difference between revisions of "Bus request line"
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'''Bus request lines''' are used in a number of [[bus]] architectures (for example, the [[UNIBUS]] and [[QBUS]]), for a [[device controller]] to communicate to the [[Central Processing Unit|CPU]] (or whatever circuitry is controlling the bus) that it is requesting an [[interrupt]] or [[Direct Memory Access|DMA]] bus cycle. | '''Bus request lines''' are used in a number of [[bus]] architectures (for example, the [[UNIBUS]] and [[QBUS]]), for a [[device controller]] to communicate to the [[Central Processing Unit|CPU]] (or whatever circuitry is controlling the bus) that it is requesting an [[interrupt]] or [[Direct Memory Access|DMA]] bus cycle. | ||
| − | The device controller does this by asserting the bus request line to the CPU, to notify it. Such lines are usually | + | The device controller does this by asserting the bus request line to the CPU, to notify it. Such lines are usually instantiated as [[wired-OR]] lines, to enable them to be used in [[broadcast]] mode. |
==See also== | ==See also== | ||
Latest revision as of 08:24, 28 July 2025
Bus request lines are used in a number of bus architectures (for example, the UNIBUS and QBUS), for a device controller to communicate to the CPU (or whatever circuitry is controlling the bus) that it is requesting an interrupt or DMA bus cycle.
The device controller does this by asserting the bus request line to the CPU, to notify it. Such lines are usually instantiated as wired-OR lines, to enable them to be used in broadcast mode.
See also
- Non-Processor Request and Grant - UNIBUS DMA request and grant lines
- DMA Request and Grant - QBUS DMA request and grant lines
