Difference between revisions of "Micro-LINC 300"
(Work in progress to reverse engineer the additions over a classic LINC.) |
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| − | The '''micro-LINC 300''' was a [[LINC]] compatible computer by SPEaR, Inc. It came with 4K memory, expandable to 32K. | + | The '''micro-LINC 300''' was a [[LINC]] compatible computer by [[SPEaR, Inc]]. It was implemented with [[Motorola]] [[Emitter-coupled logic|ECL]] parts and came with 4K memory, expandable to 32K. |
==Instruction set additions== | ==Instruction set additions== | ||
| + | |||
| + | This is mostly reverse engineered from schematics. | ||
===Memory banks=== | ===Memory banks=== | ||
| − | The [[primary memory | + | The [[primary memory]] can be up to 32K, divided into 32 1K pages. There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions take a five-bit page number. The '''Z''' register is set an instruction code that will restore the previous bank, i.e. an LMB or UMB instruction with the previous page. |
===Flag=== | ===Flag=== | ||
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===Buffered tape=== | ===Buffered tape=== | ||
| − | Tape transfers can run in parallel with the processor. There is a new tape accumulator, '''TA'''. '''MSC 4''' transfers the TA to the regular accumulator. The '''MSC 3''' instruction makes a following tape instruction not pause. The '''SKP 16''' instruction skips if the tape is busy. | + | Tape transfers can run in parallel with the processor. There is a new tape accumulator, '''TA'''. '''MSC 4''' pauses if the tape is busy, and then transfers the TA to the regular accumulator. The '''MSC 3''' instruction makes a following tape instruction not pause. The '''SKP 16''' instruction skips if the tape is busy. |
===Disable interrupts=== | ===Disable interrupts=== | ||
The '''MSC 7''' instruction disables interrupts. | The '''MSC 7''' instruction disables interrupts. | ||
Latest revision as of 15:54, 15 November 2025
The micro-LINC 300 was a LINC compatible computer by SPEaR, Inc. It was implemented with Motorola ECL parts and came with 4K memory, expandable to 32K.
Contents
Instruction set additions
This is mostly reverse engineered from schematics.
Memory banks
The primary memory can be up to 32K, divided into 32 1K pages. There are two five-bit registers, LP and UP. The LMB and UMB instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions take a five-bit page number. The Z register is set an instruction code that will restore the previous bank, i.e. an LMB or UMB instruction with the previous page.
Flag
There is an additional flag register, which is a single bit. The MSC 2 instruction sets the flag, and the MSC 12 clears it. SKP 17 skips if the flag is set.
Buffered tape
Tape transfers can run in parallel with the processor. There is a new tape accumulator, TA. MSC 4 pauses if the tape is busy, and then transfers the TA to the regular accumulator. The MSC 3 instruction makes a following tape instruction not pause. The SKP 16 instruction skips if the tape is busy.
Disable interrupts
The MSC 7 instruction disables interrupts.
