The DL10 PDP-10/PDP-11 Interface Channel connects PDP-10 mainframes to PDP-11s used as communication front ends; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's main memory, and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-CPU system. So, it could be connected to KA10s and KI10s, but only to KL10s with the optional old-style I/O busses.
On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's UNIBUS runs into the DL10 and is plugged into the DL10's backplane.
Data formats
Immediate mode
| Unused |
0 or 7 |
Unused |
Data
|
| 00
|
01
|
02
|
03
|
04
|
05
|
06
|
07
|
08
|
09
|
10
|
11
|
12
|
13
|
14
|
15
|
16
|
17
|
18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
Indirect mode
| A |
P |
1 |
Unused |
Address
|
| 00
|
01
|
02
|
03
|
04
|
05
|
06
|
07
|
08
|
09
|
10
|
11
|
12
|
13
|
14
|
15
|
16
|
17
|
18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
| A
|
Access
|
| 0
|
Read or write
|
| 1
|
Read only
|
| P
|
16-bit word position within 36-bit word
|
| 0
|
Bits 0-15
|
| 1
|
Bits 16-31
|
| 2
|
Bits 20-35
|
| 3
|
Bits 2-17
|
Pointer modes
| P |
S |
Word count |
Address
|
| 00
|
01
|
02
|
03
|
04
|
05
|
06
|
07
|
08
|
09
|
10
|
11
|
12
|
13
|
14
|
15
|
16
|
17
|
18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
Bytes are left-justified inside a 36-bit word.
| S
|
Byte size
|
| 2
|
16
|
| 3
|
12
|
| 4
|
8
|
| 5
|
7
|
| 6
|
6
|
PDP-11 control and status registers
DATO 100000 (Conditions out)
| Set 11 interrupt |
Clear 11 interrupt |
Set 10 interrupt |
Clear 10 interrupt |
Set nonex memory |
Clear nonex memory |
Set parity error |
Clear parity error |
Set word count overflow |
Clear word count overflow |
|
Error interrupt enable |
11 interrupt enable |
Interrupt assignment
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
DATI 100000 (Status)
| 11 interrupt |
|
10 interrupt |
|
Nonex memory |
|
Set parity error |
|
Word count overflow |
|
This port enabled |
|
Error interrupt enable |
11 interrupt enable |
Interrupt assignment
|
| 15
|
14
|
13
|
12
|
11
|
10
|
09
|
08
|
07
|
06
|
05
|
04
|
03
|
02
|
01
|
00
|
PDP-10 standard instructions
CONO DLB,
| Base address |
Mask for size of pointer block |
PDP-11
|
| 18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
CONO DLC,
| Clear DL10 |
Lock DL10 |
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
Priority interrupt assignment
|
| 18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
CONI DLB,
| Diag |
Diag msyn |
Diag C0 |
Diag C1 |
Diag R2 |
Diag R1 |
Diag INH CYC |
|
11-3 8K option |
11-2 8K option |
11-1 8K option |
11-0 8K option |
IOC lock on |
~IOC lock delay on |
~IOC lock 1 out |
~IOC lock 0 out |
18-bit address |
|
Got DL10 locked |
|
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
11 interrupt |
Port enable |
10 interrupt |
Priority interrupt assignment
|
| 00
|
01
|
02
|
03
|
04
|
05
|
06
|
07
|
08
|
09
|
10
|
11
|
12
|
13
|
14
|
15
|
16
|
17
|
18
|
19
|
20
|
21
|
22
|
23
|
24
|
25
|
26
|
27
|
28
|
29
|
30
|
31
|
32
|
33
|
34
|
35
|
