MG10 core memory

The MG10 was a core main memory system for the PDP-10s, principally the early KL10. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW; the access time is .67 μseconds maximum, and the cycle time is 1.0 μseconds. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by address bit 21.

It was a multi-port memory, with 8 ports per memory system: the CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.

It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The MG10 supports two-way interleaving internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized).

The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier PDP-10 memories.