M782 Interrupt Control
The M782 Interrupt Control (later versions M7820 and M7821) is a DEC FLIP CHIP which implements the 'interrupt control' function for the UNIBUS. It contains two separate interrupt circuit blocks; they can be wired to produce separate interrupts, or either can be used to provide the device with DMA capability.
It was used, usually along with an M105 Address Selector, in early PDP-11 device controllers which plugged into an SPC slot. It was also used in a number of early devices which were built out of a custom backplane and a large number of FLIP CHIPs, such as the RK11-C. Some later devices which no longer used a large number of small Flip Chips (such as the TMB11) also used it.
Contents
Revisions
The grant-passing circuity is quite different between the M7820 and M7821; it is possible that it was changed to reduce a race issue, but the import of the changes is not clear.
The M7821 appears in three etch revisions: the early one, marked 'M7821B'; the C, which is rare; and the D. It is not known what the difference is, but again, it may relate to race issues between interrupt requests and grants; the D contains a number of delay lines not present on the earlier models.)
Jumpers
The boards contained a number of jumpers which could be used to set confguration options.
Vectors
One set of jumpers controls the interrupt vector. The M782 can set vector address bits 3-7 (i.e. vectors from 0 through 0374); bit 2 (04) is controlled by the device's circuitry. The M7820 adds bit 8 (0400; i.e. vectors of the form 0xx0 and 0xx4).
(Note: The 1972 Edition of the 'Digital Logic Handbook' shows a jumper on address bit 2; however neither the prints, nor actual boards, agree with this.)
The M7821 adds a jumper on address bit 2 (04); that bit can be controlled by either the device's electronics, or the jumper. (The sense of the vector jumpers is also inverted between the M7821 and the two previous versions.)
Operation
The M7821 has a number of operational improvements over the M7820.
It will decline interrupt grants when there is a DMA request pending, reducing the DMA latency. Not all PDP-11 CPUs can handle this properly; a jumper (un-numbered; it is up near the handle) disables this behaviour when it is removed.
The A interrupt block can allow a device to do multiple DMA cycles with a single bus grant, when pin J2 is left high; grounding pin J2 signals that the DMA cycles are finished.
