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• KK11-A Cache Memory
  ...e [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit|CPU]]. Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] addr
  4 KB (553 words) - 02:36, 12 October 2022
• UNICHANNEL 15 System
  ...acts as an I/O [[front end]], partially to offload the PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did no * A data channel between the two CPUs, which allows them to interrupt each other; th
  1 KB (180 words) - 14:48, 28 November 2022
• MX15-B Memory Multiplexer
  The MX15-B allowed the PDP-11 (both the [[Central Processing Unit|CPU]], and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIB ...ers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 o
  2 KB (314 words) - 00:35, 1 December 2022
• M9312 ROM
  ...]] emulator over the console [[asynchronous serial line]], basic [[Central Processing Unit|CPU]] and [[main memory]] diagnostics, and the ability to [[bootstrap] The board used five 4-bit wide PROMs to hold the data; the DEC-supplied pre-programmed PROMs included the console emulator and di
  7 KB (1,103 words) - 11:42, 3 April 2022
• KD11-A CPU
  The '''KD11-A''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[micr * M7231 - Data Paths
  4 KB (588 words) - 05:52, 8 April 2024
• Able ENABLE
  The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] [[peripheral controller|dev ...rt [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
  9 KB (1,569 words) - 15:47, 6 February 2024
• DL10 PDP-11 Data Link
  The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communica ...]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, b
  5 KB (664 words) - 17:27, 7 November 2023
• TM10 Magnetic Tape Control
  ...F10 Data Channel]] for data transfers, to reduce the load on the [[Central Processing Unit|CPU]].
  1 KB (221 words) - 22:18, 21 April 2024
• Rubin 10-11 interface
  ...s) did not have access to the KA10's memory (unlike with the [[DL10 PDP-11 Data Link|DL10]] and [[DTE20 Ten-Eleven Interface|DTE20]], similar devices). ...particular alignment of the window on the UNIBUS side was necessary; the [[data path]] for the [[address]] must have contained an [[adder]].)
  3 KB (402 words) - 17:01, 22 March 2024
• PDP-5
  ...boards (equal to the [[word]] length of the machine) formed the [[Central Processing Unit|CPU]]. To minimize the initial basic cost, it had an [[input/output|I/ ...data.computerhistory.org/brochures/dec.pdp-5.1964.102646094.pdf Programmed Data Processor-5] - marketing brochure from DEC
  2 KB (360 words) - 20:03, 7 February 2024
• KD11-B CPU
  The '''KD11-B''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/05]] and [[PDP-11/10]] was a two-board [[microc [[Image:KD11-B M7260C.jpg|250px|right|thumb|A KD11-B M7260 Data Paths card, etch revision C]]
  11 KB (1,726 words) - 21:07, 2 July 2023
• Peripheral
  ...[[secondary storage]] which is permanently accessible; some other form of data storage, intended for off-line storage (e.g. [[magnetic tape]]); or communi ...]] or [[Direct Memory Access|DMA]] to get data in and out of the [[Central Processing Unit|CPU]] and/or [[main memory]], and [[interrupt]]s to get the CPU to pay
  1 KB (167 words) - 02:06, 16 December 2018
• Word
  ...n computer architecture, a word may denote data processed by the [[Central Processing Unit|CPU]], an instruction, an address, or the unit by which [[main memory]
  957 bytes (151 words) - 11:41, 11 August 2023
• IBM 704
  ...ww-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP704.html 704 Data Processing System] - IBM Archive page
  2 KB (278 words) - 02:11, 9 August 2022
• Front end
  .... saving [[register]] contents) can be significant, particularly for small data items, so avoiding bothering the main CPU with this cost (often larger in a ...n CPU, a technique used in the PPUs of the [[CDC 6600]], the [[DL10 PDP-11 Data Link|DL10]]-[[PDP-11]] combination of the [[PDP-10]] family, etc.
  1 KB (236 words) - 21:53, 23 September 2022
• NORD-OPS
  ...running under SINTRAN, providing the user with the possibility of [[batch processing]] [[job]]s and / or activities in "conversational mode" while they use SINT [[Category: Norsk Data Software]]
  1 KB (171 words) - 15:06, 9 September 2022
• Xerox Alto
  The Alto's 16-bit-wide [[Central Processing Unit|CPU]] was [[microcode]]d (which resulted in it being called the machin ...RAM]] microcode memory. (The basic ROM microcode more or less emulated a [[Data General]] [[Nova]].) Some Alto IIs supported a second 1KW of PROM microcode
  6 KB (863 words) - 22:39, 3 October 2023
• Multi-port memory
  ...e physically separately connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[channel]]s, [[Direct Memory Access|DMA]] [[device controller ...ntention ever happens (since each port has its own private copy of all the data). If more than one port can write, however, contention may arise in the wri
  1 KB (192 words) - 16:36, 15 December 2018
• UNIVAC I
  ...ords each (to reduce access times over fewer, larger lines). The [[Central Processing Unit|CPU]] operated in digit-serial mode (i.e. a digit at a time), to match ...nly [[input/output]] devices were [[magnetic tape]] units, the 'UNISERVO'. Data could be transferred to and from tape with off-line [[peripheral]]s which a
  2 KB (319 words) - 01:12, 12 July 2023
• Punched card
  ...[[secondary storage|data storage]] in the early period of computer usage. Data was stored in them by the presence, or absence, of holes punched in pre-det ...became a world-wide colossus before World War II on its dominance of card processing.
  2 KB (279 words) - 16:45, 5 December 2023

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