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- ...h automagically corrects single-[[bit]] errors, (at a 70 nsec penalty in [[access time|response time]] when an error occurs) and detects double-bit errors. T The [[access time]] is normally 490-525 nsec (typical/max; 620-675 nsec extra on [[memor3 KB (473 words) - 20:02, 30 July 2023
- ...automagically correct single-[[bit]] errors, and (at a slight penalty in [[access time|response time]] when an error occurs) detect double-bit errors.694 bytes (101 words) - 15:54, 6 February 2024
- #Redirect [[Random Access Memory]]34 bytes (4 words) - 16:41, 21 October 2018
- ...er architecture, long mode is the mode where a 64-bit operating system can access 64-bit instructions and registers. ... Real mode or virtual 8086 mode progr3 KB (536 words) - 16:57, 19 January 2023
- * [[hardware port]] - a means of gaining access to a computer or a sub-system275 bytes (40 words) - 13:11, 19 December 2023
- A '''port''', in [[hardware]] is a means of gaining access to a computer or a sub-system.473 bytes (79 words) - 04:30, 13 December 2018
- ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].1 KB (184 words) - 21:59, 8 March 2023
- | average access time = 62.5 msec1 KB (156 words) - 00:32, 15 August 2023
- ...Unit|CPU]]; they are connected to [[peripheral]]s, and usually have direct access to [[main memory]]. ...inframe]] systems; on smaller machines, mechanisms such as [[Direct Memory Access|DMA]] from [[device controller]]s do a lot of what a channel does.1 KB (205 words) - 17:18, 9 April 2024
- ...n pairs of [[contact]]s (which are connected to other pins, for electrical access). How many pairs, and whether they are open or closed when incoming voltage1 KB (167 words) - 05:08, 14 December 2018
- ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].1,023 bytes (148 words) - 13:05, 12 November 2023
- That socket gives the FPF11 access to both the [[data bus]] and the [[microinstruction]] bus on the CPU card.2 KB (383 words) - 02:31, 12 October 2022
- ...ious expansions, originally 'Mathematics and Computation'; later 'Multiple Access Computer', 'Machine Aided Cognition', and 'Man and Computer' were added) wa788 bytes (105 words) - 10:22, 10 January 2024
- | average access time = 16.9msec (60Hz), 20.3msec (50Hz)2 KB (258 words) - 22:12, 14 August 2023
- | average access time = 8.5 msec (60Hz), 10.2 msec (50Hz)3 KB (488 words) - 18:37, 14 August 2023
- ...chip also contains [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.5 KB (773 words) - 22:42, 20 December 2023
- ...ox]] holding a pair of [[DR11-B parallel interface]]s (the [[Direct Memory Access|DMA]] type of DR11 - one for [[packet]] input, and one for output), and a c3 KB (338 words) - 04:19, 30 August 2022
- ...the [[UNIBUS]], either for an [[interrupt]], or performing [[Direct Memory Access|DMA]].2 KB (386 words) - 01:41, 6 July 2023
- #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]68 bytes (7 words) - 01:49, 6 December 2018
- #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]68 bytes (7 words) - 01:50, 6 December 2018