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- ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen.2 KB (378 words) - 19:15, 7 July 2023
- ...open architecture member of the KFKI TPA-family. With a microcoded central processing unit, the speed and performance is due to its efficient instruction set and ...lates the 30-bit SBI addresses to 18-bit UNIBUS addresses, handles DMA and data buffering (The UBA does 4 UNIBUS-cycles on one SBI cycle).4 KB (587 words) - 00:38, 2 January 2024
- ...y simple. The [[operating system]]'s [[kernel]] (both [[instruction]]s and data) permanently occupies low physical memory; [[process]]es reside above the k ...for one or two (see below) large block(s) containing the kernel's code and data; details of the kernel's address space and main memory layout are given bel7 KB (1,161 words) - 15:20, 8 July 2023
- ...PU]] provide nice [[flow chart]]s for the [[microcode]] in these [[Central Processing Unit|CPUs]]; with one tiny exception, the microcode in the two is identical | 026 || 9-I || 322 || Fetch index data31 KB (3,760 words) - 05:02, 5 November 2022
- Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, Œ, trademark. MDS(R) is a registered trademark of Mohawk Data Sciences890 KB (107,817 words) - 03:20, 3 January 2024
- o Concurrent Processing of Multiple Applications of memory beyond 640KB for applications and data. End users will50 KB (7,113 words) - 03:35, 17 December 2018
- Library of Congress Cataloging in Publication Data British Cataloging in publication Data available627 KB (92,395 words) - 03:42, 17 December 2018
- ...ped in the Fall of 1975, was DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPU]], introducing the [[QBUS]], and using the [[LSI-11 chip set]]. It ...component side facing the viewer) is [[KEV11]], μROM 1, μROM 0, Control, Data Path.3 KB (411 words) - 22:06, 20 December 2023
- ...s]], using the same [[LSI-11 chip set]]. It contains only the [[Central Processing Unit|CPU]], and nothing else; it is otherwise identical in functionality to ...ips (from the handle end) is, in fact, [[KEV11]], Control, uROM 1, uROM 0, Data Path (per the KD11-HA print set); the order given in the Handbook is that f2 KB (336 words) - 18:34, 19 July 2023
- void data type, and several bug fixes. The cc command including ged, a graphical editor, and numerous data113 KB (13,419 words) - 02:06, 17 December 2018
- * G110 - [[DEC card form factor|hex-width]] memory control logic and data channels ...planes wired to hold one or more MM11-L sets, in addition to the [[Central Processing Unit|CPU]].5 KB (841 words) - 07:14, 25 March 2022
- The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins ...] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which5 KB (868 words) - 23:38, 9 April 2022
- It used four 4-bit wide [[PROM]]s to hold the data. The board occupied [[address]]es 773000-773776 and 765000-765776; a config Other configuration switches controlled which address the [[Central Processing Unit|CPU]] jumped to on power on (a clever kludge, controlled by another co9 KB (1,304 words) - 19:41, 7 December 2021
- The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' (' ...alled; they connect to the E Bus (for control), and also to the C Bus (for data movement). The [[MASSBUS]] can be used to connect a variety of [[disk]] and11 KB (1,737 words) - 13:06, 2 April 2024
- ...eripheral Controller|SPC]] slot in the same [[backplane]] as the [[Central Processing Unit|CPU]], and a 20-[[conductor]] [[flat cable]] which connected the two. ...d, a 6-digit [[Light Emitting Diode|LED]] display which showed address and data information, several individual indicator LEDs, and the following function7 KB (1,114 words) - 20:56, 24 October 2022
- .../70]] computers ([[KB11-A CPU|KB11-A]] and [[KB11-B CPU|KB11-B]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was the progenitor of the se * M8113 Exponent and Data Path1 KB (201 words) - 02:17, 13 October 2022
- ...uters (the later [[KB11-D CPU|KB11-D]] and [[KB11-C CPU|KB11-C]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was [[program compatible]] w * M8129 Exponent and Data Path1 KB (209 words) - 02:18, 13 October 2022
- ...roduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit|CPU]] and a [[KTJ11-B UNIBUS adapter|KTJ11-B]] [[UNIBUS]] adapter to c ...[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can re4 KB (731 words) - 17:11, 6 February 2024
- ...although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit|CPU]]'s address space) at any one time. ...anently dedicating scarce memory space in the Exec's address space to such data, or ii) having to change a number of page table entries in the Exec mode pa15 KB (2,571 words) - 22:23, 11 October 2022
- The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User' An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called9 KB (1,311 words) - 18:10, 2 July 2023
