QBUS
The QBUS, previously known as the "LSI-11 bus", was intended as a cheaper alternative to the UNIBUS system by Digital Equipment Corporation.
It was widely used in PDP-11s and VAXen.
The bus had multiplexed address and data lines, and was available in 16-, 18-, and 22-address-bit configurations (data width remained 16 bits in all three versions).
Important note: The 16-bit and 18/22-bit backplanes are electrically incompatible and mixing the two may damage cards on the bus.
It is possible to upgrade 18-bit backplanes to 22-bit; see Upgrading QBUS backplanes.
Signalling
Like the UNIBUS, there are three basic kinds of cycles on the QBUS: data read/write cycles (in which a 'master' reads or writes data to/from a 'slave', which is usually, but not always, memory); DMA cycles (in which a device gains control of the bus so that it can do a read/write cycle); and interrupt cycles, in which a device causes the CPU to perform an interrupt.
All QBUS transactions are asynchronous, and use interlocked request/response signals for control and timing.
Pinout
QBUS pins are identified in the standard UNIBUS manner; there are two connectors, A and B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet', A-V, with G, I, O and Q dropped.
By signal
| Signal | Pin | Signal | Pin |
|---|---|---|---|
| Ground | AJ1 | BDAL00 | AU2 |
| Ground | AM1 | BDAL01 | AV2 |
| Ground | AT1 | BDAL02 | BE2 |
| Ground | AC2 | BDAL03 | BF2 |
| Ground | BJ1 | BDAL04 | BH2 |
| Ground | BM1 | BDAL05 | BJ2 |
| Ground | BT1 | BDAL06 | BK2 |
| Ground | BC2 | BDAL07 | BL2 |
| +5 | AA2 | BDAL08 | BM2 |
| +5 | BV1 | BDAL09 | BN2 |
| +5 | BA2 | BDAL10 | BP2 |
| +5B | AE1 * | BDAL11 | BR2 |
| +5B | AS1 * | BDAL12 | BS2 |
| +5B | AV1 | BDAL13 | BT2 |
| +12 | AD2 | BDAL14 | BU2 |
| +12 | BD2 | BDAL15 | BV2 |
| +12B | AS1 * | BDAL16 | AC1 |
| +12B | BS1 | BDAL17 | AD1 |
| -12 | AB2 | BDAL18 | BC1 |
| -12 | BB2 | BDAL19 | BD1 |
| BDAL20 | BE1 | ||
| ASpare2 | BU1 | BDAL21 | BF1 |
| MSpareA | AK1 | ||
| MSpareB | AL1 | BBS7 | AP2 |
| MSpareB | BK1 | BDIN | AH2 |
| MSpareB | BL1 | BDOUT | AE2 |
| PSpare1 | AU1 | BREF | AR1 |
| PSpare2 | BU1 | BRPLY | AF2 |
| PSpare4 | BS1 | BSACK | BN1 |
| SSpare1 | AE1 * | BSYNC | AJ2 |
| SSpare2 | AF1 | BWTBT | AK2 |
| SSpare3 | AH1 * | BDMGI | AR2 |
| SSpare8 | BH1 | BDMGO | AS2 |
| BDMR | AN1 | ||
| BDCOK | BA1 | BIAKI | AM2 |
| BEVNT | BR1 | BIAKO | AN2 |
| BHALT | AP1 | BIRQ4 | AL2 |
| BINIT | AT2 | BIRQ5 | AA1 |
| BPOK | BB1 | BIRQ6 | AB1 |
| SRUN | AH1 * | BIRQ7 | BP1 |
Signals marked with a "*" show cases where two signals use the same pin (not at the same time, obviously).
By pin
| Signal | Pin | Note | Signal | Pin | Note |
|---|---|---|---|---|---|
| BIRQ5 | AA1 | old BSpare1 | +5 | AA2 | |
| BIRQ6 | AB1 | old BSpare2 | -12/-5 | AB2 | |
| BDAL16 | AC1 | old BSpare3 | Ground | AC2 | |
| BDAL17 | AD1 | old BSpare4 | +12 | AD2 | |
| SSpare1 | AE1 | alt +5B | BDOUT | AE2 | |
| SSpare2 | AF1 | alt SRUN/SMENBL on CF1 | BRPLY | AF2 | |
| SSpare3 | AH1 | alt SRUN on CH1 | BDIN | AH2 | |
| Ground | AJ1 | BSYNC | AJ2 | ||
| MSpareA | AK1 | BWTBT | AK2 | ||
| MSpareB | AL1 | BIRQ4 | AL2 | was BIRQ | |
| Ground | AM1 | BIAKI | AM2 | ||
| BDMR | AN1 | BIAKO | AN2 | ||
| BHALT | AP1 | BBS7 | AP2 | ||
| BREF | AR1 | BDMGI | AR2 | ||
| +5B/+12B | AS1 | old PSpare3 | BDMGO | AS2 | |
| Ground | AT1 | BINIT | AT2 | ||
| PSpare1 | AU1 | BDAL00 | AU2 | ||
| +5B | AV1 | BDAL01 | AV2 | ||
| BDCOK | BA1 | +5 | BA2 | ||
| BPOK | BB1 | -12/-5 | BB2 | ||
| BDAL18 | BC1 | old SSpare4 | Ground | BC2 | |
| BDAL19 | BD1 | old SSpare5 | +12 | BD2 | |
| BDAL20 | BE1 | old SSpare6 | BDAL02 | BE2 | |
| BDAL21 | BF1 | old SSpare7 | BDAL03 | BF2 | |
| SSpare8 | BH1 | BDAL04 | BH2 | ||
| Ground | BJ1 | BDAL05 | BJ2 | ||
| MSpareB | BK1 | BDAL06 | BK2 | ||
| MSpareB | BL1 | BDAL07 | BL2 | ||
| Ground | BM1 | BDAL08 | BM2 | ||
| BSACK | BN1 | BDAL09 | BN2 | ||
| BIRQ7 | BP1 | old PSpare6 | BDAL10 | BP2 | |
| BEVNT | BR1 | BDAL11 | BR2 | ||
| PSpare4/+12B | BS1 | BDAL12 | BS2 | ||
| Ground | BT1 | BDAL13 | BT2 | ||
| PSpare2 | BU1 | BDAL14 | BU2 | ||
| +5 | BV1 | BDAL15 | BV2 |
References to pin "Cxy" refer to a quad-wide slot (e.g. as used by the original LSI-11 CPU board).
