CDC 6600
| CDC 6600 | |
| Manufacturer: | Control Data Corporation |
|---|---|
| Year Announced: | September, 1964 |
| Year First Shipped: | 1965 |
| Form Factor: | mainframe |
| Word Size: | 60 bits |
| Clock Speed: | 10 MHz |
| Memory Size: | 128K words (max) |
| Memory Speed: | 1 μsecond (cycle time) |
| Physical Address Size: | 17 bits |
| Memory Management: | base and bounds |
| Operating System: | SCOPE. KRONOS |
| Predecessor(s): | none |
| Successor(s): | CDC 7600 |
| Price: | US$2.4M |
The CDC 6600 was an influential early (1964) mainframe computer. It is generally considered the first supercomputer, three times faster then the IBM 7030 Stretch, the previous 'fastest computer' record-holder; the 6600 held the title from 1965 to 1969. It was the first computer to use a superscalar internal architecture (although the term 'superscalar' did not exist at that time).
It used a RISC-like approach, in that instructions were simple, doing only one thing; the instruction set was basically load-store. Instructions took a minimum of three clock ticks.
It had ten independent 'functional units' in the CPU:
- branch
- boolean
- shift
- long integer add
- floating point add
- floating point multiply (two)
- floating point divide
- incrementers (two; also performed memory operations)
Each instruction was routed to the appropriate functional unit, which, if idle, could begin executing right away. (For the duplexed functional units, assignment alternated to an idle unit.) The units were not pipelined internally, a refinement that was introduced with the 6600's successor, the CDC 7600.
The CPU did not do any I/O; that was left to a set of ten 'Peripheral Processing Units', which shared access to the main memory (which had a 32-way interleave to maximize throughput).
In addition to the main memory, the 6600 was later upgraded with an 'Extended Core Storage' unit, with a cycle time of 3.2 μseconds, holding up to 2 megawords. This was intended to smooth out the large performance gap in the storage hierarchy between main memory and disk.
The 6600 was built using then-new silicon transistors, and the physical arrangement was designed to minimize conductor lengths, to minimize 'speed of light' delays.
Further reading
- Jim E. Thornton, Design of A Computer: The Control Data 6600, Scott, Foresman, Glenview, 1970
