Difference between revisions of "CDC 6600"
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| − | The '''CDC 6600''' was an influential early (1964) [[mainframe]] computer. It is generally considered the first [[supercomputer]], three times faster than the [[IBM 7030 Stretch]], the previous 'fastest computer' record-holder; the 6600 held the title from 1965 to 1969. | + | The '''CDC 6600''' was an influential early (1964) [[mainframe]] computer; the dual-[[Central Processing Unit|CPU]] version of the 6600 was denominated as a '''CDC 6700'''. It is generally considered the first true [[supercomputer]], three times faster than the [[IBM 7030 Stretch]], the previous 'fastest computer' record-holder; the 6600 held the title from 1965 to 1969. |
It was also the first computer to use a [[superscalar]] internal [[architecture]] (although the term 'superscalar' did not exist at that time). The functional units were not [[pipeline]]d internally, a refinement that was introduced with the 6600's successor, the [[CDC 7600]]. | It was also the first computer to use a [[superscalar]] internal [[architecture]] (although the term 'superscalar' did not exist at that time). The functional units were not [[pipeline]]d internally, a refinement that was introduced with the 6600's successor, the [[CDC 7600]]. | ||
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It used a [[Reduced Instruction Set Computer|RISC]]-like approach, in that [[instruction]]s were simple, doing only one thing; the [[instruction set]] was basically [[load-store architecture|load-store]]. Instructions took a minimum of three clock ticks. | It used a [[Reduced Instruction Set Computer|RISC]]-like approach, in that [[instruction]]s were simple, doing only one thing; the [[instruction set]] was basically [[load-store architecture|load-store]]. Instructions took a minimum of three clock ticks. | ||
| − | The [[Central Processing Unit|CPU]] did not do any [[input/output|I/O]]; that was left to a set of ten 'Peripheral Processing Units', which shared access to the [[main memory]] (which had a 32-way [[interleaving|interleave]] to maximize throughput). | + | The [[Central Processing Unit|CPU]] did not do any [[input/output|I/O]]; that was left to a set of ten 'Peripheral Processing Units', which shared access to the [[main memory]] (which had a 32-way [[memory interleaving|interleave]] to maximize throughput). |
In addition to the main memory, the 6600 was later upgraded with an 'Extended Core Storage' unit, with a [[cycle time]] of 3.2 µseconds, holding up to 2 megawords. This was intended to smooth out the large performance gap in the [[storage hierarchy]] between main memory and [[disk]]. | In addition to the main memory, the 6600 was later upgraded with an 'Extended Core Storage' unit, with a [[cycle time]] of 3.2 µseconds, holding up to 2 megawords. This was intended to smooth out the large performance gap in the [[storage hierarchy]] between main memory and [[disk]]. | ||
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* Second Order Conflict: a conflict where one operand of an instruction is the output of a previous instruction, which has not yet completed - these were dealt with by not letting the given functional unit start its processing until its input was available. | * Second Order Conflict: a conflict where one operand of an instruction is the output of a previous instruction, which has not yet completed - these were dealt with by not letting the given functional unit start its processing until its input was available. | ||
* Third Order Conflict: one where an instruction will use as an output register one which is an input to a previous, but as-yet un-started instruction - these are handled by holding the result in the functional unit until it can safely be stored. | * Third Order Conflict: one where an instruction will use as an output register one which is an input to a previous, but as-yet un-started instruction - these are handled by holding the result in the functional unit until it can safely be stored. | ||
| + | |||
| + | {{semi-stub}} | ||
==Further reading== | ==Further reading== | ||
| − | * Jim E. Thornton, ''Design of A Computer: The Control Data 6600'', Scott, Foresman, Glenview, 1970 | + | * Jim E. Thornton, [http://www.bitsavers.org/pdf/cdc/cyber/books/DesignOfAComputer_CDC6600.pdf ''Design of A Computer: The Control Data 6600''], Scott, Foresman, Glenview, 1970 <!-- |
| + | alt - https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC272/S2005/Papers/Thornton-DesignOfAComputer_CDC6600.pdf --> | ||
| + | * Jim E. Thornton, [https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC272/S2005/Papers/6600-Thornton_64.pdf ''Parallel Operation in the Control Data 6600''], AFIPS Proc. FJCC, Vol. 26, 1964 | ||
| + | |||
| + | ==External links== | ||
| − | + | * [http://bitsavers.org/pdf/cdc/cyber/ Cyber] - CDC 6600 documentation at [[Bitsavers]] | |
| + | ** [http://bitsavers.org/pdf/cdc/cyber/cyber_70/thornton_6600_paper.pdf Considerations in Computer Design - Leading up to the Control Data 6600] | ||
| + | ** [http://bitsavers.org/pdf/cdc/cyber/cyber_70/60100000AL_6000_Series_Computer_Systems_HW_Reference_Aug78.pdf Control Data 6000 Series Computer Systems Hardware Reference Manual] | ||
| + | * [http://bitsavers.org/pdf/cdc/Tom_Hunter_Scans/ Scans] - additional 6000 Series documents | ||
| + | ** [http://bitsavers.org/pdf/cdc/Tom_Hunter_Scans/6000_Series_Computer_Systems_RefMan_Jul65.pdf Control Data 6000 Series Computer Systems Reference Manual] - considerably earlier version | ||
| + | * [http://ygdes.com/CDC/60100000D_6600refMan_Feb67.pdf Control Data 6400/6500/6600/ Computer Systems Reference Manual] | ||
| + | * [https://people.computing.clemson.edu/~mark/cdc6600.html CDC 6600 Links] | ||
| + | * [http://gordonbell.azurewebsites.net/Computer_Structures__Readings_and_Examples/00000509.htm Parallel operation in the Control Data 6600] | ||
| − | [[Category: | + | [[Category: Supercomputers]] |
| + | [[Category: 60-bit Computers]] | ||
Latest revision as of 17:26, 22 January 2024
| CDC 6600 | |
| Manufacturer: | Control Data Corporation |
|---|---|
| Year Announced: | September, 1964 |
| Year First Shipped: | 1965 |
| Form Factor: | mainframe |
| Word Size: | 60 bits |
| Clock Speed: | 10 MHz |
| Memory Size: | 128K words (max) |
| Memory Speed: | 1 µsecond (cycle time) |
| Physical Address Size: | 17 bits |
| Memory Management: | base and bounds |
| Operating System: | SCOPE, KRONOS |
| Predecessor(s): | none |
| Successor(s): | CDC 7600 |
| Price: | US$2.4M |
The CDC 6600 was an influential early (1964) mainframe computer; the dual-CPU version of the 6600 was denominated as a CDC 6700. It is generally considered the first true supercomputer, three times faster than the IBM 7030 Stretch, the previous 'fastest computer' record-holder; the 6600 held the title from 1965 to 1969.
It was also the first computer to use a superscalar internal architecture (although the term 'superscalar' did not exist at that time). The functional units were not pipelined internally, a refinement that was introduced with the 6600's successor, the CDC 7600.
It used a RISC-like approach, in that instructions were simple, doing only one thing; the instruction set was basically load-store. Instructions took a minimum of three clock ticks.
The CPU did not do any I/O; that was left to a set of ten 'Peripheral Processing Units', which shared access to the main memory (which had a 32-way interleave to maximize throughput).
In addition to the main memory, the 6600 was later upgraded with an 'Extended Core Storage' unit, with a cycle time of 3.2 µseconds, holding up to 2 megawords. This was intended to smooth out the large performance gap in the storage hierarchy between main memory and disk.
The 6600 was built using then-new silicon transistors, and the physical arrangement was designed to minimize conductor lengths, to minimize 'speed of light' delays. All the longer wires in the system were transmission lines, for more reliable operation.
Superscalar details
It had ten independent 'functional units' in the CPU:
- branch
- boolean
- shift
- long integer add
- floating point add
- floating point multiply (two)
- floating point divide
- incrementers (two; also performed memory operations)
Each instruction was routed to the appropriate functional unit, which, if idle, could begin executing right away. (For the duplexed functional units, assignment alternated to an idle unit.)
The CPU had to detect all conflicts between two instructions which it was attempting to execute simultanously; this was done in hardware by the 'Unit and Register Reservation Control' (usually called the 'Scoreboard').
It detected and dealt with three kinds of conflicts:
- First Order Conflict: a conflict which requires the use of the same functional unit (for the ones which were not duplexed), or output register - these were dealt with by stalling instruction processing.
- Second Order Conflict: a conflict where one operand of an instruction is the output of a previous instruction, which has not yet completed - these were dealt with by not letting the given functional unit start its processing until its input was available.
- Third Order Conflict: one where an instruction will use as an output register one which is an input to a previous, but as-yet un-started instruction - these are handled by holding the result in the functional unit until it can safely be stored.
Further reading
- Jim E. Thornton, Design of A Computer: The Control Data 6600, Scott, Foresman, Glenview, 1970
- Jim E. Thornton, Parallel Operation in the Control Data 6600, AFIPS Proc. FJCC, Vol. 26, 1964
External links
- Cyber - CDC 6600 documentation at Bitsavers
- Scans - additional 6000 Series documents
- Control Data 6000 Series Computer Systems Reference Manual - considerably earlier version
- Control Data 6400/6500/6600/ Computer Systems Reference Manual
- CDC 6600 Links
- Parallel operation in the Control Data 6600
