Difference between revisions of "Extended Memory Interconnect"

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The '''Extended Memory Interconnect''' (usually given as the acronym: '''XMI''') was a [[bus]] introduced with the [[VAX 6000 series]] of [[Digital Equipment Corporation|DEC]] computers to cope with increased requirements, e.g bandwidth.
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[[File:VAX 6200 Four-Processor System Block Diagram.png|thumb|400px|rightt|A four-processor VAX 6200 system built around an XMI bus]]
  
== XMI Overview ==
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The '''Extended Memory Interconnect''' (usually given as the acronym: '''XMI''') was a [[bus]] introduced with the [[VAX 6000 series]], and also used in other later [[Digital Equipment Corporation|DEC]] [[VAX]] computers, to cope with increased requirements, e.g bandwidth.
The XMI is the primary interconnect for the [[VAX 6000 Model 200|VAX 6200]] system. The XMI supports multiple processors, multiple memory modules, and multiple I/O adapters.  
 
  
Figure 2-1 shows a four-processor VAX 6200 system.
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It supports multiple processors, multiple [[main memory]] memory modules, and multiple I/O adapters; the overall system built around an XMI bus thus forms a tightly-coupled [[multi-processor]]. The bus has special capabilities to support the shared access to memory required by such a system.
  
[[File:VAX 6200 Four-Processor System Block Diagram.png]]
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The XMI is the primary interconnect for the [[VAX 6000 Model 200|VAX 6200]] system (as shown to the side).
  
The XMI consists of the electrical environment of the XMI bus, the protocol observed by a node on the bus, the backplane, and the logic used to implement the protocol.
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==Overview==
  
The XMI bus is limited length, pended, and synchronous with centralized arbitration. Several transactions can be in progress at a given time, allowing highly efficient use of the bus bandwidth. Arbitration and data transfers can occur simultaneously.
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The constituent elements of the XMI bus are:
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* the [[analog]] electrical element of the bus,
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* the [[protocol]] observed by a node on the bus,
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* the [[backplane]], and
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* the [[logic]] used to implement the protocol.
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The XMI is of limited length, is [[synchronous]], and has centralized [[arbitration]] (individual [[bus grant line]]s run from the [[arbitrator]] to each slot in the backplane). Arbitration and data transfers use logically separate divisions of the bus, so they can occur in parallel.
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It is also 'pended', which means that an operation can be left in an incomplete state, to allow other entities to use the bus, before resuming, and finishing. Several transactions can thus be in progress at any time, rather than forcing later operations to wait for the completion of an earlier operation before they can begin; this allows highly efficient use of the bus bandwidth.
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The XMI supports:
  
The bus supports:
 
 
* Quadword-, octaword-, and hexword-length reads to memory
 
* Quadword-, octaword-, and hexword-length reads to memory
 
* Quadword- and octaword-length memory writes
 
* Quadword- and octaword-length memory writes
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The longword operations implement byte and word modes required by certain I/O devices.  
 
The longword operations implement byte and word modes required by certain I/O devices.  
  
The XMI has a 64 ns bus cycle.
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It has a 64 ns bus cycle, and a bandwidth of 100 Mbytes per second; however, the usable bandwidth depends on transaction length:
 
 
The XMI has a bandwidth of 100 Mbytes per second; however, the usable bandwidth depends on transaction length:
 
  
 
{| class="wikitable"
 
{| class="wikitable"
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|}
 
|}
  
== XMI Versions ==
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==XMI versions==
The XMI bus started with the "+5V '''XMI-1'''" version which was developed to the "+3.3V '''XMI-2'''" version later on.
 
 
 
There was an upgrade kit option H9657-CU that takes a VAX 6000 Model 200, 300, or 400 system with an XMI-1 power system and upgrades it to a VAX 6000 Model 500 with an XMI-2 power system.
 
  
The upgrade adds +3.3 volt power, an XMI-2 [[backplane]] preassembled with bus bars and cables, and an H7206-B power and logic unit.  
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The XMI bus started with the "+5V '''XMI-1'''" version, which was developed to the "+3.3V '''XMI-2'''" version later.
  
The manual [http://www.vaxhaven.com/images/f/fc/EK-650EB-UP-002.pdf EK-650EB-UP-002 VAX 6000 XMI Conversion Manual] describes the upgrade procedure.  
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There was an upgrade kit, option H9657-CU, which takes a VAX 6000 Model 200, 300, or 400 system with an XMI-1 power system, and upgrades it to a VAX 6000 Model 500, with an XMI-2 power system. The upgrade adds +3.3 volt power, an XMI-2 backplane pre-assembled with bus bars and cables, and an H7206-B power and logic unit.  
  
 
{{semi-stub}}
 
{{semi-stub}}
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==External links==
 
==External links==
  
* [http://www.bitsavers.org/pdf/dec/vax/6200/EK-620AA-TM-001_Tech_May88.pdf VAX 6200 Technical User's Guide] (EK-620AA-TM-001) - the XMI is covered in Chapter 2, pp. 37-91 of the PDF
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* [http://www.bitsavers.org/pdf/dec/vax/6200/EK-620AA-TM-001_Tech_May88.pdf VAX 6200 Technical User's Guide] (EK-620AA-TM-001) - the XMI is covered in Chapter 2 (pp. 37-91 of the PDF)
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* [http://www.vaxhaven.com/images/f/fc/EK-650EB-UP-002.pdf EK-650EB-UP-002 VAX 6000 XMI Conversion Manual]
  
 
[[Category: DEC Buses]]
 
[[Category: DEC Buses]]
 
[[Category: XMI]]
 
[[Category: XMI]]
 
[[Category: VAXen]]
 
[[Category: VAXen]]

Latest revision as of 13:44, 20 March 2023

A four-processor VAX 6200 system built around an XMI bus

The Extended Memory Interconnect (usually given as the acronym: XMI) was a bus introduced with the VAX 6000 series, and also used in other later DEC VAX computers, to cope with increased requirements, e.g bandwidth.

It supports multiple processors, multiple main memory memory modules, and multiple I/O adapters; the overall system built around an XMI bus thus forms a tightly-coupled multi-processor. The bus has special capabilities to support the shared access to memory required by such a system.

The XMI is the primary interconnect for the VAX 6200 system (as shown to the side).

Overview

The constituent elements of the XMI bus are:

  • the analog electrical element of the bus,
  • the protocol observed by a node on the bus,
  • the backplane, and
  • the logic used to implement the protocol.

The XMI is of limited length, is synchronous, and has centralized arbitration (individual bus grant lines run from the arbitrator to each slot in the backplane). Arbitration and data transfers use logically separate divisions of the bus, so they can occur in parallel.

It is also 'pended', which means that an operation can be left in an incomplete state, to allow other entities to use the bus, before resuming, and finishing. Several transactions can thus be in progress at any time, rather than forcing later operations to wait for the completion of an earlier operation before they can begin; this allows highly efficient use of the bus bandwidth.

The XMI supports:

  • Quadword-, octaword-, and hexword-length reads to memory
  • Quadword- and octaword-length memory writes
  • Longword-length read and write operations to I/O space

The longword operations implement byte and word modes required by certain I/O devices.

It has a 64 ns bus cycle, and a bandwidth of 100 Mbytes per second; however, the usable bandwidth depends on transaction length:

Usable XMI Bandwidth
Operation Bandwidth (Mbytes/second)
Longword (4 bytes) Read 31.25
Quadword (8 bytes) Read 62.50
Octaword (16 bytes) Read 83.30
Hexword (32 bytes) Read 100.00
Longword Write 31.25
Quadword Write 62.50
Octaword Write 83.30

XMI versions

The XMI bus started with the "+5V XMI-1" version, which was developed to the "+3.3V XMI-2" version later.

There was an upgrade kit, option H9657-CU, which takes a VAX 6000 Model 200, 300, or 400 system with an XMI-1 power system, and upgrades it to a VAX 6000 Model 500, with an XMI-2 power system. The upgrade adds +3.3 volt power, an XMI-2 backplane pre-assembled with bus bars and cables, and an H7206-B power and logic unit.

External links