Difference between revisions of "Floating point accelerator"
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| − | A '''floating point accelerator''' is a (usually optional) unit for [[Central Processing Unit|CPUs]] which provides extra [[ | + | A '''floating point accelerator''' is a (usually optional) unit for [[Central Processing Unit|CPUs]] which provides extra [[logic]] to speed up [[floating point]] operations. In [[microcode]]d CPUs, floating point [[instruction]]s are performed in microcode, but an operation such as a floating point multiply can take many microinstructions. A floating point accelerator provides additional computing hardware which allows floating point instructions to be executed more quickly, increasing the processing power of the CPU, but without any changes to the [[instruction set architecture]] (so existing [[object code]] will run much faster, without needing any changes). |
Examples include the [[FPF11 floating point processor]] for the [[KDF11 CPUs]]; full PDP-11 [[FP11 floating point]] is provided by the [[KEF11-A floating point chip]] (which implements it using microcode), but the FPF11 replaces that implementation, and provides higher performance. Most [[VAX]] CPUs have optional floating point accelerators available for them, too. | Examples include the [[FPF11 floating point processor]] for the [[KDF11 CPUs]]; full PDP-11 [[FP11 floating point]] is provided by the [[KEF11-A floating point chip]] (which implements it using microcode), but the FPF11 replaces that implementation, and provides higher performance. Most [[VAX]] CPUs have optional floating point accelerators available for them, too. | ||
Latest revision as of 01:20, 8 July 2022
A floating point accelerator is a (usually optional) unit for CPUs which provides extra logic to speed up floating point operations. In microcoded CPUs, floating point instructions are performed in microcode, but an operation such as a floating point multiply can take many microinstructions. A floating point accelerator provides additional computing hardware which allows floating point instructions to be executed more quickly, increasing the processing power of the CPU, but without any changes to the instruction set architecture (so existing object code will run much faster, without needing any changes).
Examples include the FPF11 floating point processor for the KDF11 CPUs; full PDP-11 FP11 floating point is provided by the KEF11-A floating point chip (which implements it using microcode), but the FPF11 replaces that implementation, and provides higher performance. Most VAX CPUs have optional floating point accelerators available for them, too.
