Difference between revisions of "MA20 core memory"

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* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00010_MA20_Schematic_Jul76.pdf MA20 Field Maintenance Print Set] (MP00010)
* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00010_MA20_Schematic_Jul76.pdf MA20 Field Maintenance Print Set] (MP00010)
[[Category: PDP-10 memories]]
[[Category: PDP-10 Memories]]

Latest revision as of 14:45, 22 April 2022

The MA20 was a core main memory system for the later PDP-10s, principally the mid-period KL10; it connected to the KL10's so-called internal memory bus, the S-Bus. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; parity is provided to protect the memory contents. The access time is 1.00 µseconds, and the cycle time is 1.92 µseconds (both for the first word in a 4-word block, using four-way interleaving).

Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

See also

External links