View source for MSV11-M QBUS memory

[[Image:MSV11-M.jpg|thumb|250px|right|MSV11-MB card]]

The '''MSV11-M''' (M7506) is a [[DEC card form factor|dual]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs  [[integrated circuit|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.

The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It is a [[QBUS#Variable address size|Q22]] card; it reportedly supports QBUS block mode.

==Configuration==

No documentation on the MSV11-M is extant, so it is currently not known how to configure it. The purpose of the two-position jumper between E19 (apparently a [[delay line]]) and E18 is currently unknown.
<!-- A single 6-position [[Dual Inline Package|DIP]] switch configures the card's 22-bit starting address:
* Switches S3-S4 must always be OFF;
{| class="wikitable"
! S1 || S2 || Staring Address
|-
| OFF || OFF || 00000000 (0 MB)
|-
| OFF || ON ||  04000000 (1 MB)
|-
| ON || OFF || 10000000 (2 MB)
|-
| ON || ON || 14000000 (3 MB)
|} -->

==Control Register==

Each board has a single control [[register]], which can be configured in the range 17772100-17772136, using the set of four jumpers between chips E27 and E26. They are not numbered on the board; for our purposes we will number them W1-W4, starting with the left-hand jumper, with the board oriented with the insertion handles at the top.  

{| class="wikitable"
! W4 !! W3 !! W2 !! W1 !! CSR Address
|-
| In || In || In || In || 17772100
|-
| In || In || In || Out || 17772102
|-
| In || In || Out || In || 17772104
|-
| In || In || Out || Out || 17772106
|-
| In || Out || In || In || 17772110
|-
| In || Out || In || Out || 17772112
|-
| In || Out || Out || In || 17772114
|-
| In || Out || Out || Out || 17772116
|-
| Out || In || In || In || 17772120
|-
| Out || In || In || Out || 17772122
|-
| Out || In || Out || In || 17772124
|-
| Out || In || Out || Out || 17772126
|-
| Out || Out || In || In || 17772130
|-
| Out || Out || In || Out || 17772132
|-
| Out || Out || Out || In || 17772134
|-
| Out || Out || Out || Out || 17772136
|}
<!--In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
{{16bit-header}}
| ''Parity Error'' || Extended Error Address Enable || colspan=2 | Reserved || colspan=7 | ''Error Address'' || colspan=2 | Reserved || Write Wrong Parity || Reserved || Parity Error Enable 
{{16bitoctal-bitout}}
The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit; when it holds the low address ('Extended Error Address Enable' is 0), it holds address bits 11 through 17; when it holds the high address ('Extended Error Address Enable' is 1), it holds bits 21 through 18 - bits 11-9 of the register are unused. -->

==Technical information==

As far as is known, there are no copies of the engineering drawings extant for the MSV11-M.<!--However, some technical information, enough to [[repairing un-documented MOS memory boards|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.
As described above, each board has 2 banks in the array of DRAM chips; with 256K chips, each bank is thus 512KB. (Note that when writing data, the MSV11-R sends a 'write' [[signal]] to ''all'' the banks, and selects the one to ''actually'' use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)
The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.
Thus, for example, bit 0 of bank 0 is in chip E197. The full table is:
{| class="wikitable"
! Bit !! Bank 0 !! Bank 1 !! Bank 2 !! Bank 3 !! Bank 4 !! Bank 5 !! Bank 6 !! Bank 7
|-
| 01 || E197 || E196 || E195 || E194 || E193 || E192 || E191 || E190
|-
| 02 || E189 || E188 || E187 || E186 || E185 || E184 || E183 || E182
|-
| 04 || E180 || E179 || E178 || E177 || E176 || E175 || E174 || E173
|-
| 10 || E172 || E171 || E170 || E170 || E169 || E168 || E167 || E166
|-
| 20 || E164 || E163 || E162 || E161 || E160 || E159 || E158 || E157
|-
| 40 || E155 || E154 || E153 || E152 || E151 || E150 || E149 || E148
|-
| 100 || E147 || E146 || E145 || E144 || E143 || E142 || E141 || E140
|-
| 200 || E139 || E138 || E137 || E136 || E135 || E134 || E133 || E132
|-
| 400 || E114 || E113 || E112 || E111 || E110 || E109 || E108 || E107
|-
| 1000 || E105 || E104 || E103 || E102 || E101 || E100 || E99 || E98
|-
| 2000 || E97 || E96 || E95 || E94 || E93 || E92 || E91 || E90
|-
| 4000 || E89 || E88 || E87 || E86 || E85 || E84 || E83 || E82
|-
| 10000 || E81 || E80 || E79 || E78 || E77 || E76 || E75 || E74
|-
| 20000 || E72 || E71 || E70 || E70 || E69 || E68 || E67 || E66
|-
| 40000 || E64 || E63 || E62 || E61 || E60 || E59 || E58 || E57
|-
| 100000 || E56 || E55 || E54 || E53 || E52 || E51 || E50 || E49
|-
| Low byte Parity || E
|-
| High byte Parity || E
|}-->
<!-- ''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.
The following 256K DRAM chips have been observed to be used: MB81256-15 (Fujitsu). M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments)
Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage. -->

==Further reading==

* ''MSV11-M User Guide'', EK-MSV1M-UG
* ''MSV11-M Field Maintenance Printset'' (MP-02053 - not online)

{{PDP-11}}

[[Category: QBUS Memories]]