Difference between revisions of "Non Return to Zero"
From Computer History Wiki
(+serial line use) |
(add example) |
||
| Line 3: | Line 3: | ||
In NRZ, whether a particular [[bit]] is '0' or '1' is indicated by the [[signal]] level during each [[clock]] time; in other words, there is no 'rest' state between bits. | In NRZ, whether a particular [[bit]] is '0' or '1' is indicated by the [[signal]] level during each [[clock]] time; in other words, there is no 'rest' state between bits. | ||
| − | The disadvantage of NRZ is that a long strings of either value do ''not'' cause any level transitions (hence the name), so a separate clock is always needed, because it cannot be self-clocking (unless used with a periodic explicit clock, or with either [[bit stuffing]] or [[run-length limited coding]], to limit the maximum number of transition-less bit times). | + | The disadvantage of NRZ is that a long strings of either value do ''not'' cause any level transitions (hence the name), so a separate clock is always needed, because it cannot be self-clocking (unless used with a periodic explicit clock, as in [[asynchronous serial line]]s; or with either [[bit stuffing]] or [[run-length limited coding]], to limit the maximum number of transition-less bit times). |
| + | |||
| + | {{semi-stub}} | ||
==See also== | ==See also== | ||
* [[Non Return to Zero Inverted|NRZI]] | * [[Non Return to Zero Inverted|NRZI]] | ||
| − | |||
| − | |||
| − | |||
[[Category: Theory]] | [[Category: Theory]] | ||
Latest revision as of 22:50, 23 May 2022
Non Return to Zero (usually given as the acronym, NRZ) is an encoding technique which is commonly used on magnetic storage and serial lines.
In NRZ, whether a particular bit is '0' or '1' is indicated by the signal level during each clock time; in other words, there is no 'rest' state between bits.
The disadvantage of NRZ is that a long strings of either value do not cause any level transitions (hence the name), so a separate clock is always needed, because it cannot be self-clocking (unless used with a periodic explicit clock, as in asynchronous serial lines; or with either bit stuffing or run-length limited coding, to limit the maximum number of transition-less bit times).
