Difference between revisions of "PDP-6"
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| logic type = germanium and silicon [[transistor]]s | | logic type = germanium and silicon [[transistor]]s | ||
| design type = asynchronous with hardware subroutines | | design type = asynchronous with hardware subroutines | ||
| − | | clock speed = 4 μsec | + | | clock speed = 4 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous) |
| memory speed = 5 μsec (inital), 2 μsec (later) | | memory speed = 5 μsec (inital), 2 μsec (later) | ||
| memory mgmt = single base and bounds register pair | | memory mgmt = single base and bounds register pair | ||
| Line 20: | Line 20: | ||
| price = US$120K (CPU), US$300K (system) | | price = US$120K (CPU), US$300K (system) | ||
}} | }} | ||
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| + | [[Image:PDP-6 mod top.jpg|thumb|left|300px|A System Module used in a [[PDP-6]]; this example has had its [[transistor]]s salvaged from it]] | ||
The '''PDP-6''' was effectively the first model of the [[PDP-10]]; they are (mostly) binary-code compatible. It was built out of [[System Module]]s, [[DEC]]'s predecessor to the [[FLIP CHIP]] module series (out of which the first PDP-10, the [[KA10]], was built). | The '''PDP-6''' was effectively the first model of the [[PDP-10]]; they are (mostly) binary-code compatible. It was built out of [[System Module]]s, [[DEC]]'s predecessor to the [[FLIP CHIP]] module series (out of which the first PDP-10, the [[KA10]], was built). | ||
Revision as of 00:13, 6 August 2017
| PDP-6 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | March, 1963 |
| Year First Shipped: | June, 1964 |
| Year Discontinued: | 1965 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | germanium and silicon transistors |
| Design Type: | asynchronous with hardware subroutines |
| Clock Speed: | 4 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous) |
| Memory Speed: | 5 μsec (inital), 2 μsec (later) |
| Physical Address Size: | 18 bits |
| Virtual Address Size: | 18 bits |
| Memory Management: | single base and bounds register pair |
| Operating System: | Monitor, ITS |
| Predecessor(s): | None |
| Successor(s): | KA10 |
| Price: | US$120K (CPU), US$300K (system) |
The PDP-6 was effectively the first model of the PDP-10; they are (mostly) binary-code compatible. It was built out of System Modules, DEC's predecessor to the FLIP CHIP module series (out of which the first PDP-10, the KA10, was built).
The machine was not a success, commercially (only 23 were sold), in part because the hardware was unreliable (largely because of one type of large System Module, which contained one bit of the entire ALU section of the CPU - a 'bridge too far' at the then-current state of printed circuit board technology).
