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  • | transfer rate = 1.2 Mbytes/sec ...surface. It was internally operated by a [[microprocessor]] which used 32-bit burst [[error-correcting code|ECC]] to invisibly repair simple data errors.
    2 KB (332 words) - 03:16, 31 August 2023
  • | transfer rate = 1.2 Mbytes/sec | tracks = 561 (18-bit word mode)<br>559 (16-bit word mode)
    3 KB (355 words) - 16:23, 18 August 2023
  • | transfer rate = 2.4 Mbytes/sec ...It was internally operated by a pair of [[microprocessor]]s, which used 32-bit burst [[error-correcting code|ECC]] to invisibly repair simple data errors.
    2 KB (306 words) - 03:12, 31 August 2023
  • Data transfer rate 0.625 MB/S int Bytes/Sector 256 spin-up W ECC Bit -
    19 KB (2,330 words) - 14:58, 5 January 2024
  • a minimal rate SLOWSCAN, which gives the desired number of rate at which the clock algorithm is run increases linearly
    57 KB (8,582 words) - 03:00, 17 January 2023
  • od New options O, X, and D print 32 bit integers in the clock scan rate in revolutions-per-minute now
    39 KB (5,307 words) - 05:01, 11 December 2018
  • 3.4.2 Bit Test and Modify Instructions 3.4.3 Bit Scan Instructions
    890 KB (107,817 words) - 03:20, 3 January 2024
  • The very first generation of microcomputers were 8-bit machines, such When 16-bit microprocessors were first announced, Microsoft knew that
    627 KB (92,395 words) - 03:42, 17 December 2018
  • ...l line interface|EIA RS-232]] connectivity at speeds of 110 to 9600 [[baud rate|baud]] (the range depended on the version); the DL11-E version also provide ...sition dial selectors (one for transmit, one for receive) which selected a rate:
    7 KB (1,055 words) - 17:22, 6 February 2024
  • .../data bit (FM); 2 usec/data bit (MFM) (diskette to drive buffer); 1.2 usec/bit (uffer to CPU interface) | words per sector = 64 16-bit
    8 KB (1,195 words) - 20:09, 15 August 2023
  • ...ifferent sizes, but normally were all 256 words; a tape could hold 128K 12-bit words. * Reading/writing rate - 25K lines/second (40 micro-seconds/line)
    3 KB (519 words) - 02:13, 28 February 2024
  • ...t, or 128 36-bit words. A tape could hold 184K 12-bit words, or 144K 16/18-bit words. * Reading/writing rate - 30K lines/second (33-1/3 micro-seconds/line)
    5 KB (736 words) - 14:21, 30 May 2022
  • | CPU-clock-rate = 114MHz [[#ref_1|[1]]] | Memory-checking = 7-bit ECC/longword [[#ref_2|[2]]]
    1 KB (135 words) - 08:20, 12 September 2023
  • ...ated at 10 Mbits/second; it has since been refined to support higher [[bit rate]]s and longer link distances (but see 'Parameter contention' below). Follow The 48-bit physical address of the DIX Ethernet is known as the [[Media Access Control
    8 KB (1,199 words) - 22:00, 5 October 2023
  • | transfer rate = 7.4 usec/18-bit word | words per sector = 256 18-bit
    2 KB (299 words) - 20:41, 10 February 2024
  • ...his allows twice as many bits to be encoded for a given maximum transition rate. ...bit time for a '1', and no reversal for a '0'. A reversal ''between'' data bit times occurs with consecutive zeros.
    788 bytes (130 words) - 11:52, 14 July 2022
  • ...ock time); for a '1', there is an additional reversal in the middle of the bit time, with no reversal indicating a '0'. ...ersal between data bit times; consecutive ones show two reversals in every bit time (i.e. doubling the frequency of reversals; hence the name).
    729 bytes (122 words) - 21:21, 14 December 2018
  • ...ain a circular selector switch in the upper left corner to select the baud rate of the built-in serial line; also, the position of the large [[UART]] chip ...savers.org/pdf/dec/pdp11/1105/1105_RevAH_Engineering_Drawings_Jul76.pdf 16 bit computer (PDP 1105) engineering drawings, Revision AH] (covers the KD11-B o
    11 KB (1,726 words) - 21:07, 2 July 2023
  • The Alto was novel, for its time, in that each machine had a [[bit-mapped display]], allowing the creation of a [[graphical user interface]], ...long with four PCBs for [[main memory]] (in a 64KW [[address space]] of 16-bit [[word]]s), and those for [[device controller]]s such as the [[disk]], disp
    6 KB (863 words) - 22:39, 3 October 2023
  • ...option which provides a [[line time clock]], producing [[interrupt]]s at a rate of 50 or 60 Hz, driven from the [[alternating current|AC]] power provided t ...every clock cycle (and causes an interrupt when that happens, if the other bit is set).
    1 KB (219 words) - 01:58, 8 February 2022

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