Search results
From Computer History Wiki
Create the page "Phase" on this wiki! See also the search results found.
Page title matches
- '''Phase Encoding''' (usually given as the acronym, '''PE''') is an [[encoding]] tec1 KB (248 words) - 16:25, 20 April 2024
- #Redirect [[Phase Encoding]]28 bytes (3 words) - 18:16, 12 February 2024
- #Redirect [[Phase Encoding]]28 bytes (3 words) - 18:21, 20 April 2024
- #Redirect [[Phase Encoding]]28 bytes (3 words) - 18:22, 20 April 2024
- #Redirect [[Phase Encoding]]28 bytes (3 words) - 18:23, 20 April 2024
Page text matches
- ==='''Phase I''' (1974)=== ==='''Phase II''' (1976)===17 KB (2,405 words) - 17:43, 13 January 2024
- |7.1||1981 December||First release of RSTS/E supporting DECnet Phase III. |9.3||1986 December||First release of RSTS/E supporting DECnet Phase IV.14 KB (2,134 words) - 16:06, 3 May 2023
- '''Setting up DECnet phase IV on VMS''' is a fairly straightforward procedure. Note: Before setting up any system I recommend you read up on [[DECnet Phase IV basics]].3 KB (447 words) - 22:03, 17 August 2022
- The bus BDAL17 line is driven during the data read phase of a read cycle to indicate that the addressed entity (usually main memory)13 KB (2,043 words) - 23:27, 14 January 2024
- <!-- | power consumption = 660 VA per phase (running); 3300 VA per phase(starting) -->3 KB (492 words) - 00:27, 15 August 2023
- ...the end) and a [[sync]] bit. A spare set of 3 timing tracks, recorded in [[phase]] with the primaries, provided redundancy for the 3 primaries..1 KB (212 words) - 22:14, 14 August 2023
- ...e redundant VSS pin, and requring a two-phase clock input instead of a one-phase clock input and two clock outputs, room was made to include four signals P08 KB (1,369 words) - 17:59, 25 June 2021
- HECnet is basically a DECnet phase IV network. Currently, the main router is a PDP-113 KB (507 words) - 12:05, 4 March 2022
- The recording density, of either 1600 bpi (using [[Phase Encoding|PE]] [[encoding]]) or 800 bpi (using [[Non Return to Zero Inverted2 KB (230 words) - 03:37, 22 April 2024
- 1) How would you typically debug the kernel during the development phase?28 KB (4,805 words) - 18:01, 29 February 2024
- ...By 1954 NUSSE was considered sufficiently stable to go to the operational phase, and was moved to the ''Norwegian Computing Centre'' ([[NCC]]).4 KB (647 words) - 20:59, 18 March 2024
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes13 KB (2,064 words) - 18:04, 5 August 2017
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes14 KB (2,318 words) - 06:15, 1 September 2018
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames16 KB (2,460 words) - 12:02, 6 September 2021
- IBM will phase out of OS/2 altogether, one way or another. Note that they21 KB (3,783 words) - 03:41, 17 December 2018
- *** [https://multicians.org/phase-one.html Phase One]9 KB (1,331 words) - 17:05, 7 March 2024
- == PCI phase == This phase is trickey as you have to do a lot of foot work, but I find the PCI stuff w8 KB (1,323 words) - 01:27, 21 January 2023
- And we'll be into the GUI phase of the install. Since we've got an AMD PCnet driver in the floppy drive we5 KB (947 words) - 11:21, 9 June 2023
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames13 KB (1,865 words) - 18:41, 3 July 2022
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as6 KB (1,042 words) - 22:50, 1 May 2022
- -c Suppress the loading phase of the compilation, and4 KB (707 words) - 14:59, 26 October 2009
- -c Suppresses the loading phase of the compilation, as3 KB (432 words) - 17:28, 26 October 2009
- Several; the non-obvious one is `Phase error', which means4 KB (626 words) - 18:36, 26 October 2009
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes14 KB (2,267 words) - 16:59, 5 April 2010
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes15 KB (2,380 words) - 18:46, 28 October 2020
- ...[[PDP-11]] and [[VAX]] computers. Its recording density of 1600 bpi used [[Phase Encoding|PE]] [[encoding]], and it used the [[Pertec tape interface]].3 KB (355 words) - 14:55, 22 April 2024
- # For example 0 x07 is normal, black white; 0 x70 is reversed - phase, black white14 KB (1,991 words) - 01:23, 20 December 2018
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames2 KB (225 words) - 04:17, 17 December 2018
- during this phase... :-)25 KB (3,017 words) - 18:47, 13 January 2024
- And we'll be into the GUI phase of the install.6 KB (997 words) - 11:22, 9 June 2023
- Powered by a single-phase AC:6 KB (853 words) - 00:41, 2 January 2024
- ...s of WD. By the way, rk-shnyh drives three-phase (!) Food, they have three-phase spindle motor akkurat ... The fact that the CMEA countries flogged PDP-11,1 KB (229 words) - 07:45, 29 October 2022
- The TU78 supported two data formats: [[Phase Encoding]] (PE) or [[Group Coded Recording]] (GCR). Bit density wss 1600 bi2 KB (313 words) - 22:25, 21 April 2024
- <!-- | power consumption = 660 VA per phase (running); 3300 VA per phase(starting) -->4 KB (533 words) - 17:08, 15 August 2023
- | power consumption = 660 VA per phase (running); 3300 VA per phase (starting, 10 seconds max)2 KB (297 words) - 00:39, 15 August 2023
- The recording density, of either 1600 bpi (using [[Phase Encoding|PE]] [[encoding]]) or 6250 bpi (using [[Group Coded Recording|GCR]3 KB (409 words) - 20:32, 23 April 2024
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames5 KB (848 words) - 07:12, 2 February 2016
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames57 KB (8,582 words) - 03:00, 17 January 2023
- Intel provides field systems engineering services for any phase of your In the second phase of address transformation, the 80386 transforms a890 KB (107,817 words) - 03:20, 3 January 2024
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames6 KB (835 words) - 13:57, 29 May 2020
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames44 KB (6,192 words) - 09:30, 29 September 2023
- ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames7 KB (1,100 words) - 07:32, 2 February 2016
- We are going to use the following config file to start the first phase of the installation. Save the following configuration into a file such as ** Phase 1 - Check Blocks and Sizes13 KB (2,077 words) - 16:30, 7 August 2017
- * φ1: The Phase 1 output from the two-phase non-overlapping clock of the processor * <u>φ2</u>: The inverted Phase 2 output from the two-phase non-overlapping clock of the processor, used to indicate the presence of va6 KB (1,084 words) - 16:55, 16 February 2024
- *11 - Non-Simple reference (phase 1) *12 - Non-Simple reference (phase 0)15 KB (2,571 words) - 22:23, 11 October 2022
- * PGM(13) (10-1): Window access (phase 1)? * PGM(14) (10-1): Window access (phase 0)?31 KB (4,983 words) - 18:22, 2 July 2023
- ...pe density = 800 bpi ([[Non Return to Zero Inverted|NRZI]])<br>1600 bpi ([[Phase Encoded|PE]])5 KB (729 words) - 17:48, 20 April 2024
- ...(125 IPS). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).2 KB (366 words) - 18:41, 22 May 2022
- ...r second). It can handle 800 bits/inch ([[NRZI]]) and 1600 bits/inch (PE - Phase Encoded).2 KB (345 words) - 18:27, 22 May 2022
- ...ne-independent intermediate language called OCODE, generated by the second phase, into the target machine's [[object code]]. Porting the compiler involved writing a new third phase; compiling that with the existing compiler on the host machine, producing a3 KB (542 words) - 07:42, 20 June 2023