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- | bus arch = [[UNIBUS]]/FastBus ...[[multi-port memory|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was implemented as part of the CPU6 KB (895 words) - 23:52, 29 February 2024
- ...logically connect several [[peripheral]]s over the same set of wires. Each bus defines its set of [[connector]]s to physically plug devices, cards or cabl ...ology, or connected by switched hubs, as in the case of [[Universal Serial Bus|USB]].14 KB (2,170 words) - 05:09, 5 September 2019
- ...support higher [[bit rate]]s and longer link distances (but see 'Parameter contention' below). Follow-on versions have been produced at 100 and 1000 ('Gigabit Et ...s a [[Carrier-Sense Multiple Access with Collision Detection]] (CSMA-CD) [[bus]] (i.e. a shared [[broadcast]] channel on which all stations can hear any s8 KB (1,199 words) - 22:00, 5 October 2023