Difference between revisions of "Three cycle data break"
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| − | + | '''Three cycle data break''' was a form of [[Direct Memory Access|DMA]] to [[main memory]] used on a number of [[List of Programmed Data Processors|early DEC computers]]. | |
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| + | The [[buffer]] address and word count were kept in main memory (at an [[address]] often specified by [[jumper]]s on the [[peripheral]]). This required the assistance of the [[Central Processing Unit|processor]] to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word. | ||
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| + | This moved some of common [[logic]] (needed to implement the I/O device) from each I/O device into one shared set of hardware within the processor, thereby economizing on the hardware in the device. The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation). | ||
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| + | [[Category: DEC Hardware]] | ||
Revision as of 01:32, 14 May 2021
Three cycle data break was a form of DMA to main memory used on a number of early DEC computers.
The buffer address and word count were kept in main memory (at an address often specified by jumpers on the peripheral). This required the assistance of the processor to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
This moved some of common logic (needed to implement the I/O device) from each I/O device into one shared set of hardware within the processor, thereby economizing on the hardware in the device. The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).
