Difference between revisions of "VAX Bus Interconnect"
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The primary internal functions of the VAXBI are to do priority [[arbitration]] for use of the bus (fully distributed among all the nodes, with no 'master' node), and transfer data between the sub-systems, as well as carrying [[interrupt]]s. It is also used for a variety of lesser functions, such as initialization, etc. Some transactions on the VAXBI, such as interrupts, may be both single-responder and multi-responder. | The primary internal functions of the VAXBI are to do priority [[arbitration]] for use of the bus (fully distributed among all the nodes, with no 'master' node), and transfer data between the sub-systems, as well as carrying [[interrupt]]s. It is also used for a variety of lesser functions, such as initialization, etc. Some transactions on the VAXBI, such as interrupts, may be both single-responder and multi-responder. | ||
| − | Data transfers can range from 1-16 bytes, in units of 1, 2 or 4 four-byte [[word]]s. The VAXBI is [[synchronous]] and [[clock]]ed (like the [[Synchronous Backplane Interconnect|SBI]] of the [[VAX-11/780]]). [[Cache]] operation is integrated into the operations on the VAXBI. | + | Data transfers can range from 1-16 bytes, in units of 1, 2 or 4 four-byte [[word]]s. The VAXBI is [[synchronous]] and [[clock]]ed (like the [[Synchronous Backplane Interconnect|SBI]] of the [[VAX-11/780]]). [[Cache]] operation is integrated into the operations on the VAXBI. [[Bandwidth]] provided is 13.3 MB/sec. |
The VAXBI had 52 signal lines in total; of these, a group of 32 lines are shared between [[address]] and data (like the earlier [[QBUS]]). [[Parity]] is used to protect both of these during transfer over the VAXBI. | The VAXBI had 52 signal lines in total; of these, a group of 32 lines are shared between [[address]] and data (like the earlier [[QBUS]]). [[Parity]] is used to protect both of these during transfer over the VAXBI. | ||
At the [[analog]] level, it is [[wired-OR]] (unlike its predecessor in the [[VAX-11/750]], the [[CPU/Memory Interconnect|CMI]], which was [[tri-state]]). [[Digital Equipment Corporation|DEC]] produced a custom [[integrated circuit|IC]] to interface to the VAXBI, implementing all the bus [[protocol]]s, leaving node designers free to concentrate on the design of their item. | At the [[analog]] level, it is [[wired-OR]] (unlike its predecessor in the [[VAX-11/750]], the [[CPU/Memory Interconnect|CMI]], which was [[tri-state]]). [[Digital Equipment Corporation|DEC]] produced a custom [[integrated circuit|IC]] to interface to the VAXBI, implementing all the bus [[protocol]]s, leaving node designers free to concentrate on the design of their item. | ||
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| + | ==VAXBI cards== | ||
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| + | * [[DEBNT]] | ||
==External links== | ==External links== | ||
Latest revision as of 04:46, 13 January 2024
The VAX Bus Interconnect (often given as VAXBI) is the main bus in mid-range and high-end VAXen. In some machines, it connects all the main sub-systems, such as main memory and the CPU (including multi-processors); in the others, it is only used to support the I/O adapters and peripherals.
Machines which used it included the VAX 8200 through the VAX 8800. For the 8200 and VAX 8300 it performed all the functions listed above; for the others, it only supported the peripherals and I/O adapters. One of the latter was produced for the UNIBUS; peripherals included Ethernet and CI interfaces.
The VAXBI can hold up to 16 'nodes' (the formal term for VAXBI participating devices). No slot is specialized; any node can go into any slot.
The primary internal functions of the VAXBI are to do priority arbitration for use of the bus (fully distributed among all the nodes, with no 'master' node), and transfer data between the sub-systems, as well as carrying interrupts. It is also used for a variety of lesser functions, such as initialization, etc. Some transactions on the VAXBI, such as interrupts, may be both single-responder and multi-responder.
Data transfers can range from 1-16 bytes, in units of 1, 2 or 4 four-byte words. The VAXBI is synchronous and clocked (like the SBI of the VAX-11/780). Cache operation is integrated into the operations on the VAXBI. Bandwidth provided is 13.3 MB/sec.
The VAXBI had 52 signal lines in total; of these, a group of 32 lines are shared between address and data (like the earlier QBUS). Parity is used to protect both of these during transfer over the VAXBI.
At the analog level, it is wired-OR (unlike its predecessor in the VAX-11/750, the CMI, which was tri-state). DEC produced a custom IC to interface to the VAXBI, implementing all the bus protocols, leaving node designers free to concentrate on the design of their item.
VAXBI cards
External links
- VAX Hardware Handbook Volume 2 - the VAXBI is mentioned on page 1-5 (pg. 14 of the PDF) and 2-23—2-24 (pp. 46-47 of the PDF)
- VAXBI - documentation at Bitsavers
- VAXBI System Reference Manual (EK-VBISY-RM-003)
- VAXBI Adapters Student Guide (EY-5554E-SG-0002)
