Am29000
The Am29000 is a family of 32-bit RISC CPUs from AMD. As a RISC system, it has a load-store architecture.
It was rooted in the work at Berkeley which produced other RISC CPUs such as the SPARC. Work on the initial model, the 29000, started in 1984–1985; it was announced in March, 1987, and released in May, 1988. The initial Am29000 was followed by several other versions, including the 29050 in October, 1990, and ending with the 29040 in 1995.
One major novelty in the hardware design was that it was a so-called Harvard architecture machine; there were separate ports on the chip for instructions and data, intended to be attached to separate main memory banks. (This allows each bank to be customized for the expected memory reference patterns - sequential for instructions.) Internally, it uses a four-stage pipeline, but it can still execute one instruction every clock cycle.
