Packard Bell PB 250
The Packard Bell PB 250 (variously also given as PB-250 and PB250 in contemporary documentation) was an early low-cost (and thus low-performance) all-transistor computer, produced by Packard Bell Computer (later by Raytheon, after Packard Bell Electronics' computer division was acquired by them in 1964). Design began in November, 1959, and it was first delivered in October, 1960.
Its chief designer was Max Palevsky (later of Scientific Data Systems). The PB 250 was apparently a descendant of the Bendix G-15; Palevsky had worked on the DA-1 differential analyzer option for the G-15 while he was employed by Bendix, before he helped to start Packard Bell. Stanley Frankel, who had done the LGP-30, a very similar machine, consulted on the design; the PB 250 seems to have been influenced by the LGP-30 also (no doubt via Frankel).
It was a serial computer, which used magnetostrictive delay lines for its main memory. The basic memory held 10 'long lines', each containing 256 words (somewhat confusingly called 'sectors'), which were 22 bits wide. Up to 53 additional lines may be added. (Line 037 is reserved for the 'index register', below.) Any 256-word line may be replaced by a shorter line, such as a 16-word line, for decreased access time (at the cost of a reduction in available space); line 0 is usually configured this way. Line 037 is a single-word line. 16K words of core memory was available as an option; all memory was protected with parity.
Like the G-15 on which it was apparently based, it was capable of optimum programming; although the version on the PB 250 was more restricted. With no waiting, it could perform a peak of 83,00 additions per second, and about 3,600 multiplications per second (depending on the operands).
Standard input/output equipment included a Flexowriter, which included a paper tape reader and punch. Optional equipment included a high-speed paper tape reader and punch, a punched card reader and punch, up to 6 magnetic tape drives, and a variety of analog-digital units.
A digital differential analyzer, the Transistorized Realtime Incremental Computer Expandable (TRICE), was available as a co-processor for solving certain types of problems. Also available was the Hycomp 250, where analog computers, such as the TR10 or TR48 from EAI, were connected to a PB 250 to form a hybrid computer.
Internals
The PB 250's instructions were also 22 bits wide; it was a single-address machine. They contained 5 fields:
| Field Name | Width | Description |
|---|---|---|
| Sector Number | 8 | Operand 'sector' number |
| Sequence Tag | 1 | Use optimum coding for address of next instruction |
| Operation Code | 6 | |
| Line Number | 6 | Operand 'line' number |
| Index Tag | 1 | Use index register |
The PB 250 had about 51 operation codes (a complete table may be found at the end of 'PB 250: A High Speed Serial General Purpose Computer Using Magnetostrictive Delay Line Storage', below). In some instructions (e.g. shift instructions), the Sector and Line Number fields do not contain addresses, but immediate operands. If the index register is used, it is not a classic index register; the address in it substitutes for the address in the instruction.
The optimum coding of the PB 250 was somewhat restricted: if the 'Sequence Tag' bit in an instruction was set, the next instruction executed was the next instruction read in the current line; with it clear, the numerically next (i.e. the one in the 'sector' one larger than that of the current instruction) instruction was the next one executed. Instructions are executed at a rate of 300 per second in the sequential address mode, and about 40,000 per second in the sequential storage mode. Control could be passed to a different line (a jump) with a specific instruction. Some instructions, which do not use the 'Sector Number' to specify an operand, use it to indicate the location of the next instruction.
The machine was fairly simple (which contributed to the low cost); it contained only 375 transistors, and 32 flip-flops:
| Flop | Function |
|---|---|
| F1-F5 | Pulse time counter |
| Ec, Rc | Instruction phase |
| Is | Comparison detector during fetch |
| Oc, O6-O1 | Opcode of current instruction |
| L5-L1 | Operand line register |
| K3-K1 | Command line register |
| Sc | Carry for sector counter |
| Ca | Carry for adder |
| Of | Overflow |
| Pc | Parity |
| Ae, Be, Ce | Register shift |
| Bf, Tf | Reader and typewriter control |
The machine contained three single-word 'registers', implemented by short delay lines; they were denominated as A, B, and C. A and B could be joined together into a double-width register for some instructions.
Further reading
- Robert Mark Beck, PB 250: A High Speed Serial General Purpose Computer Using Magnetostrictive Delay Line Storage, Eastern Joint IRE-AIEE-ACM Computer Conference, December 1960
- Max Palevsky, The PB 250 General Purpose Digital Computer, Computers and Automation, Vol. 9, No. 8B, August 1960 - pp. 1B–3B (9–11 of the PDF)
External links
- PB-250 - documentation at Bitsavers
- PB250 Programming and Reference Manual (SP-174)
- Technical Manual Volume 1 (PBC 1000)
- TRICE Theory and Maintenance Manual (CSP-151)
- Hycomp 250 — The First Desk Top Hybrid Analog/Digital Computing System (SP-182) - brochure
- PB-250 minicomputer
- The PB-250 - has a number of subsidiary pages with further images
- Packard Bell PB250
- Packard Bell PB250 s/n 135 - has several images
- PB-250
- Operations Trainer - description of use of PB 250
