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KS10 with main cabinet open; CPU at the bottom right
Manufacturer: Digital Equipment Corporation
Architecture: PDP-10
Year Introduced: 1978
Form Factor: small mainframe
Word Size: 36 bits
Logic Type: LS TTL ICs
Design Type: clocked synchronous microcoded
Microword Width: 96
Microcode Length: 2K
Clock Speed: 300 nsec (micro-cycle)
Cache Size: 512 words
Cache Speed: 300 nsec
Memory Speed: 0.9 μsec
Physical Address Size: 19 bits (some had 20)
Virtual Address Size: 18 bits
Memory Management: paging, 512-word pages
Operating System: TOPS-10, TOPS-20, ITS, TYMCOM-XX
Predecessor(s): KL10
Successor(s): None

The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture) from DEC. It was intended as a small, low-cost entry model, not as a replacement for the earlier KL10 mainframe. A few documents refer to it as the SM10, maybe "small 10".

The KS10 is organized around a synchronous bus (carried only on the main backplane), to which are attached the microcoded CPU, the main memory controller, and two or three UNIBUS adapters (which are used to perform all I/O in the system. Parity is used throughout for error detection.

These two types of bus, along with MASSBUSes provided by RH11-C's on the UNIBUSes, are the only buses in the KS10; it supports neither the PDP-10 Memory Bus nor the PDP-10 I/O Bus. Addresses and data share one set of multiplexed conductors on the KS10 internal bus; the address is transferred on one cycle, and the associated data on a following cycle.

That bus also supports interrupts from the UNIBUS adapters, as well as diagnostic access from the mandatory 'console' subsystem, which is interfaced to the KS10 bus. It contains an 8080 microprocessor controlled by a PROM, and is used to bootstrap the system, load the CPU's wholly writeable microcode, etc.

The memory is specific to the KS10; it used 7 extra bits per word to hold ECC data, for double-bit error detection and single-bit correction. It is all connected to the memory controller through a private bus, which is also present only on the main backplane.

All KS10's contain at least two UNIBUS adapters (a third is optional); one was for the disks only, the other for all other peripherals (magnetic tape, asynchronous serial lines, etc).

Internal details

The I/O instructions were completely different from the other PDP-10 models, in part because the machine only had UNIBUSes; external I/O instructions had to specify the UNIBUS address, and also which UNIBUS adapter is being used. Separate page tables mapped the UNIBUS address space into the KS10's main memory for DMA operations.

The CPU has a 512-entry memory cache; 1-way set associative on individual words. It also has 8 different sets of registers, to speed up interrupt handling. (Set 7 is reserved for use by the microcode.) The cache and register sets are all stored in the same 300 nsec register file.

The UNIBUS which is used for the disks was run in 18-bit mode (the two parity lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11-C, mounted in the main CPU rack (although apparently on its own backplane) to drive the MASSBUS to the disks. (Only MASSBUS disks were supported on that RH11-C, apparently both for performance reasons, and since 18-bit data storage was needed).

The device controllers on the second UNIBUS were mounted in a BA11-K mounting box, mounted in the main cabinet. These included a second RH11-C in DEC-supported systems, since DEC required a tape drive for loading diagnostics; the usual choice was a TU45 interfaced via a TM02.

CPU details

It was built out of LS TTL chips, along with AMD 2901 4-bit-wide bit slice chips. The CPU was on four super hex cards:

  • M8620 DPE - data path
  • M8621 DPM - data path
  • M8622 CRA - control store
  • M8623 CRM - control store

Additional super hex cards held:

  • M8616 CSL - the console (driven by an Intel 8080A), and bus arbitrator
  • M8618 MMC - main memory controller
  • M8629 MMA - DRAM memory array modules (2 to 8)
  • M8619 UBA - UNIBUS adapters (2, optionally 3)

The CPU and main memory mounted in a single backplane, consisting of two 9-slot system units wire-wrapped together:

Slot A B C D E F
1 Extra M8629 Memory
2 Extra M8629 Memory
3 Extra M8629 Memory
4 Extra M8629 Memory
5 Extra M8629 Memory
6 Extra M8629 Memory
7 M8629 Memory
8 M8629 Memory
9 M8618 Memory Controller
10 M8623 CRM Control Store
11 M8622 CRA Control Store
12 M8620 DPE Data Path
13 M8621 DPM Data Path
14 "Reserved for I/O"
15 M8619 UBA
16 M8619 Optional UBA
17 M8616 CSL Console
18 M8619 UBA

Note: There appear to be several errors in the the 'disk' RH11 section of the 'Module Utilization' chart, Figure 1-5 (page 1-9, 18 of the PDF), in the KS10 Technical Manual (EK-OKS10-TM-002):

  • The M9200 'thin' UNIBUS jumper used to connect together the two UNIBI (see here for the explanation of why this is needed) is mis-labelled "M9300" (the M9300 is a terminator).
  • The "M8014" in the UNIBUS 'A' In slot must be an M9014 (UNIBUS to 3 flat cables; the M8014 is an RLV11 board).


DEC supported both TOPS-10 and TOPS-20 on the KS10. Later, the Incompatible Timesharing System was made to run on it, and MIT had several. Tymshare ran a version of their operating system called TYMCOM-XX.

External links