UNIBUS parity

From Computer History Wiki
Jump to: navigation, search

UNIBUS parity has a somewhat complex story.

The final UNIBUS spec says parity implementation is wholly within the slave device, and only an error signal is transferred over the bus. From the pdp11 peripherals handbook, 1975 edition (pg. 5-8): "PA and PB are generated by a slave ... [it] negates PA and asserts PB to indicate a parity error ... both negated indicates no parity error. [other combinations] are conditions reserved for future use." However, the original concepts were quite different; see below.

18-bit width

The two parity lines, PA and PB, were also taken over to produce an 18 data-bit wide version of the UNIBUS for use on some of DEC's 18- and 36-bit machines, to allow use of existing secondary storage devices and device controllers on them.

The MX15-B Memory Multiplexer for the PDP-15 would accept 18-bit data over the UNIBUS from a modified controller, e.g. the RK11-E.

The UNIBUS Adaptor on the KS10 version of the PDP-10 could also operate in 18-bit mode; the RH11 MASSBUS controller there used this to support connection of MASSBUS disks and magnetic tape drives to the KS10.


Originally the UNIBUS parity functionality was planned to be different; sometime around the introduction of the PDP-11/45, DEC changed it, twice.

First version

The first version is described in the unibus interface manual, first edition (DEC-11-HIAA-D).

In there, Table 2-1 has these entries for the PA and PB lines of the UNIBUS: "Parity Available - PA ... Indicates paritied data" and "Parity Bit - PB ... Transmits parity bit". Also, at the bottom of page 2-4, we find "PA indicates that the data being transferred is to use parity, and PB transmits the parity bit. Neither line is used by the KA11 processor."

This first version was not, as far is as known, actually implemented in anything.

Second version

The second version is described in the unibus interface manual. second edition (DEC-11-HIAB-D).

There, Table 2-1 has these changed entries for PA and PB: "Parity Bit Low - PA ... Transmits parity bit, low byte" and "Parity Bit High - PB ... Transmits parity bit, high byte"; at the top of page 2-5, the text there is wholly different from the version above, including "These lines are used by the MP11 Parity Option in conjunction with parity memories such as the MM11-FP."

This version was apparently actually implemented in the MM11-F; in the MM11-F Core Memory Manual (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.