Load-store architecture

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A load-store architecture for a CPU is one in which instructions which reference main memory are limited to a single operation to that memory - either a load, or a store (hence the name).

Early computers often had load-store architectures because that approach resulted in simple instruction sets (especially on computers which had only an accumulator), and thus simple implementations. (The PDP-8 is a machine which went this direction.)

More recently, RISC computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length instructions, which made constructing pipelines easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).

CISC computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory. The object code can be denser (since instructions can do more), which was important in the core memory era, when main memory was very expensive.