MSV11-J QBUS memory
The MSV11-J (M8637) is a QBUS/PMI DRAM main memory card. As a PMI card, it uses the CD interconnect; it can therefore only be plugged into a Q/CD backplane. NOTE: Plugging an MSV11-J card into a regular Q/Q backplane will damage the MSV11-J.
It has ECC which automagically corrects single-bit errors (at a slight penalty in response time when an error occurs), and detects double-bit errors. It holds 2 Mbytes when fully populated with 256Kx1 DRAM chips, or 1 Mbyte when half-populated (the only partially-filled configuration allowed). It supports block mode on both the QBUS and PMI.
Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable CPU, such as the KDJ11-B. In systems such as the PDP-11/83, where the primary I/O bus is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the PDP-11/84, PMI is used for communication with both the CPU and the KTJ11-B UNIBUS adapter.
The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold words at even word locations, the other for those in odd; the banks are thus interleaved. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.
On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For diagnostic purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
Four versions exist:
- MSV11-JB, 1 Mbyte
- MSV11-JC, 2 Mbyte
- MSV11-JD, 1 Mbyte
- MSV11-JE, 2 Mbyte
The -JB and -JC are earlier versions, which contain an error which prevents them working properly as QBUS memories (i.e. in the PDP-11/83); they are only usable in the PDP-11/84.
When used with a KDJ11-B, the bootstrap code in its EEPROMs insists that the ECC bits are all wholly functional, otherwise it will stop with an "Error 47 - Memory CSR Error". This happens even though the board will return correct values if the main data DRAMs are fine for the locations with bad ECC bits, and the code will accept boards with bad data bits!
When the board is in diagnostic mode, it displays an unusual error where some values (exactly 25% of the 2^16) cannot be correctly written and read back. The values affected are consistent across several boards, so this is not due to component variation. The reason, and rationale (if it is not simply a bug), are currently unknown.
Each board has a single control register, which can be configured in the range 172100-172136.
In the register contents (below), all the bits can be read and written by software; most are cleared by power up and bus INIT, except the multi-function (address/CRC) bits. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the hardware in italics.
|Uncorrected error||Extended address||Set inhibit mode||Reserved||Multi-function||Single error||Inhibit mode pointer||Diagnostic mode||Disable correction||Error indication|
The multi-function field contents depend on what is being done; it is used to hold the address of an error; and also to read, and in diagnostic mode write, the ECC bits (called 'syndrome' when read, and 'check' when written).
When it holds the low address (the low/high choice is controlled by bit 14), it holds address bits 11 through 17; when it holds the high address, bits 21 through 18, and in register bit 9, address bit 1 (to tell which bank the error was in) - bits 11-10 are unused.
When it holds the ECC bits, this is the mapping from CSR bits to ECC bits:
As far as is known, there are no engineering drawings extant for the MSV11-J. However, some technical information, enough to repair boards with faulty DRAM chips, has been gathered on it, and that is made available here.
To start with, unlike other DEC boards, this board does not contain the Exx identification numbers for chips on the board. The following scheme has therefore been devised, to identify the DRAM chips for the bit to chip table below.
The DRAM chips are organized into four blocks; block 0 and 2 hold words in the even-numbered word bank, and 1 and 3 hold those in the odd-numbered word bank. With the component side of the board facing, and the metal insertion handle at the top, the pair of low-address blocks (0 and 1) are at the top of the card, and the optional pair of high-address blocks (2 and 3) are at the bottom.
The low half of the even-numbered word bank (block 0) is on the right side (denoted with an 'R'), and the low half of the odd bank (block 1) on the left ('L'). (The high half has the sides reversed, so that block 2 is on the left, and 3 on the right.) There are three columns on each side (denoted '0'-'2', with the '0' column at the left of each group). Each column contains 17 chips (denoted '0'-'16', with '0' at the top).
Chips are identified as SCRr, where 'S' is the side ('L' or 'R'), C is the column, and 'Rr' is the row. Note that not all the chips in this area are DRAM; for example, in block 1, chips L17, L27, L211, and L213 and up, are not DRAM.
|Bit||Block 0||Block 1||Block 2||Block 3|
Note: When a DRAM chip is removed, if the affected memory location is then read, that bit will be high (1), not low (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.
The following DRAM chips have been observed to be used: MT1259-12 (Micron Technologies), HM50256-15 (Hitachi), NEC 41256 (NEC Electronics), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).
Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage.
On the board M8637 Side 1 L1 50-15672-01 C1 Ga6618 2644711 2 MB Q,P-BUS MOS MEM LPWR TPB D.V0 On the metal frame P/N 1213113 M8637 EC ASICs on board are 21-24404-01 and 21-22772-01
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Clones: CM 1420