- Programmed data transfers, in which the CPU reads or writes data to the device controller;
- Program interrupt transfers. in which the controller interrupts the CPU;
- Data break transfers, the PDP-8 term for DMA.
In addition to the usual read and write operations, a data break could also do an incremement operation, where a word was read out of main memory (core at the time), incremented, and written back during the 'write back' phase of the core cycle.
There were two different forms of the data break. In the first, the three cycle data break, the word count and buffer address are stored in main memory, at an address supplied by the device (generally from hard-wired jumpers, as this mechanism was intended to economize on the hardware in the device). An operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the second, the single cycle data break, the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.
The OMNIBUS was physically implemented as a large backplane, into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.
In analog electrical terms, it was very similar to the UNIBUS; mostly bi-directional transmission lines, with a few uni-directional control lines. The terminators and voltage levels of the two were the same, and they shared driver and receiver circuitry.